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| author | Jim Wilson <wilson@gcc.gnu.org> | 1994-01-15 15:06:17 -0800 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1994-01-15 15:06:17 -0800 |
| commit | e783e4c2b3c68d9628318249a3e6f59b0e30c5de (patch) | |
| tree | 96694f0b65fc90ee60cdfa2f6b2349ca93ebf1c0 /gcc | |
| parent | 33a3539d4363baf4e94ebaac6fded4c6fddfd50f (diff) | |
| download | gcc-e783e4c2b3c68d9628318249a3e6f59b0e30c5de.zip gcc-e783e4c2b3c68d9628318249a3e6f59b0e30c5de.tar.gz gcc-e783e4c2b3c68d9628318249a3e6f59b0e30c5de.tar.bz2 | |
(smulsi3_highpart): New pattern.
(umulsi3_highpart): New pattern.
From-SVN: r6395
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index abb307f..c0ac59c 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1837,6 +1837,42 @@ "smul %1,%2,%R0\;rd %%y,%0" [(set_attr "length" "2")]) +(define_expand "smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) + (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + " +{ + if (CONSTANT_P (operands[2])) + { + emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + "smul %1,%2,%%g0\;rd %%y,%0" + [(set_attr "length" "2")]) + +(define_insn "const_smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r")) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + "smul %1,%2,%%g0\;rd %%y,%0" + [(set_attr "length" "2")]) + (define_expand "umulsidi3" [(set (match_operand:DI 0 "register_operand" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) @@ -1869,6 +1905,42 @@ "umul %1,%2,%R0\;rd %%y,%0" [(set_attr "length" "2")]) +(define_expand "umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) + (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + " +{ + if (CONSTANT_P (operands[2])) + { + emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + "umul %1,%2,%%g0\;rd %%y,%0" + [(set_attr "length" "2")]) + +(define_insn "const_umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "uns_small_int" "")) + (const_int 32))))] + "TARGET_V8 || TARGET_SPARCLITE" + "umul %1,%2,%%g0\;rd %%y,%0" + [(set_attr "length" "2")]) + ;; The architecture specifies that there must be 3 instructions between ;; a y register write and a use of it for correct results. |