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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2017-07-05 12:58:46 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2017-07-05 12:58:46 +0000 |
| commit | e60226ffa0cc0eff39141a4954a506484c17fda4 (patch) | |
| tree | 786ad1e69105d86754df7e9ea762c40395beb5db /gcc | |
| parent | e483b7b46fd2e0db7d98975b8efcc033bc6ffb7d (diff) | |
| download | gcc-e60226ffa0cc0eff39141a4954a506484c17fda4.zip gcc-e60226ffa0cc0eff39141a4954a506484c17fda4.tar.gz gcc-e60226ffa0cc0eff39141a4954a506484c17fda4.tar.bz2 | |
[Patch ARM] Remove %? string from some Advanced SIMD patterns.
Advanced SIMD patterns are not predicable, thus they should not have
%? in their output templates. Found when auditing the code for
something else. This has been in my tree for sometime , bootstrapped
and regression tested on armhf for armv7ve+simd as the architectural
base.
Applied to trunk
<DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/neon.md (fma<VCVTF:mode>4): Remove %?.
(fma<VH:mode>4_intrinsic): Likewise.
(*fmsub<VCVTF:mode>4): Likewise.
(*fmsub<VH:mode>4_intrinsic): Likewise.
regards
Ramana
From-SVN: r249999
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 10 |
2 files changed, 12 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4ea249e..c566a3a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-07-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * config/arm/neon.md (fma<VCVTF:mode>4): Remove %?. + (fma<VH:mode>4_intrinsic): Likewise. + (*fmsub<VCVTF:mode>4): Likewise. + (*fmsub<VH:mode>4_intrinsic): Likewise. + 2017-07-05 Georg-Johann Lay <avr@gjlay.de> PR target/81305 diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 0ce3fe4..33b25ff 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -678,7 +678,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" - "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -688,7 +688,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" - "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -720,7 +720,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" - "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -731,7 +731,7 @@ (match_operand:VCVTF 2 "register_operand" "w") (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" - "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "type" "neon_fp_mla_s<q>")] ) @@ -752,7 +752,7 @@ "s_register_operand" "w")] NEON_VRINT))] "TARGET_NEON && TARGET_FPU_ARMV8" - "vrint<nvrint_variant>%?.f32\\t%<V_reg>0, %<V_reg>1" + "vrint<nvrint_variant>.f32\\t%<V_reg>0, %<V_reg>1" [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")] ) |