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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2020-12-11 16:46:26 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@linaro.org> | 2020-12-11 16:48:20 +0000 |
| commit | e36ce56e81b440a97b32e527f208f26923b7aed2 (patch) | |
| tree | 87b77fe05b49d7336857e301b8ea32c5a7c253a3 /gcc | |
| parent | 78e9cfe1e29902a887853142a5e417500fe90fc8 (diff) | |
| download | gcc-e36ce56e81b440a97b32e527f208f26923b7aed2.zip gcc-e36ce56e81b440a97b32e527f208f26923b7aed2.tar.gz gcc-e36ce56e81b440a97b32e527f208f26923b7aed2.tar.bz2 | |
arm: Auto-vectorization for MVE clean condition for vand and vorr expanders
The patch restores the unconditional definition of the VDQ iterator,
and changes the conditions of the vand and vorr expanders to use
ARM_HAVE_<MODE>_ARITH.
2020-12-11 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/iterators.md (VDQ): Remove TARGET_HAVE_MVE
conditions.
* config/arm/vec-common.md (and<mode>3): Use
ARM_HAVE_<MODE>_ARITH.
(ior<mode>3): Likewise.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/iterators.md | 7 | ||||
| -rw-r--r-- | gcc/config/arm/vec-common.md | 6 |
2 files changed, 3 insertions, 10 deletions
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index f0e1d60..5fcb7af 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -147,12 +147,7 @@ (define_mode_iterator VN [V8HI V4SI V2DI]) ;; All supported vector modes (except singleton DImode). -(define_mode_iterator VDQ [(V8QI "!TARGET_HAVE_MVE") V16QI - (V4HI "!TARGET_HAVE_MVE") V8HI - (V2SI "!TARGET_HAVE_MVE") V4SI - (V4HF "!TARGET_HAVE_MVE") V8HF - (V2SF "!TARGET_HAVE_MVE") V4SF - (V2DI "!TARGET_HAVE_MVE")]) +(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) ;; All supported floating-point vector modes (except V2DF). (define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index df0a6cd..8d9c89c 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -177,14 +177,12 @@ [(set (match_operand:VDQ 0 "s_register_operand" "") (and:VDQ (match_operand:VDQ 1 "s_register_operand" "") (match_operand:VDQ 2 "neon_inv_logic_op2" "")))] - "TARGET_NEON - || TARGET_HAVE_MVE" + "ARM_HAVE_<MODE>_ARITH" ) (define_expand "ior<mode>3" [(set (match_operand:VDQ 0 "s_register_operand" "") (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "") (match_operand:VDQ 2 "neon_logic_op2" "")))] - "TARGET_NEON - || TARGET_HAVE_MVE" + "ARM_HAVE_<MODE>_ARITH" ) |