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| author | Kazu Hirata <kazu@cs.umass.edu> | 2003-01-24 16:03:14 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2003-01-24 16:03:14 +0000 |
| commit | dff23a65f632e475aa005066cb5c79d6a2bda1ac (patch) | |
| tree | ab6c14763d1316b99b7cbfeb52571623048d0f00 /gcc | |
| parent | 05739753491634830e40e088bafb8193479fbf73 (diff) | |
| download | gcc-dff23a65f632e475aa005066cb5c79d6a2bda1ac.zip gcc-dff23a65f632e475aa005066cb5c79d6a2bda1ac.tar.gz gcc-dff23a65f632e475aa005066cb5c79d6a2bda1ac.tar.bz2 | |
* config/h8300/h8300.md (*andsi3_ashift_n_lower): New.
From-SVN: r61702
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.md | 21 |
2 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 422f6d4..2949066 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2003-01-24 Kazu Hirata <kazu@cs.umass.edu> + + * config/h8300/h8300.md (*andsi3_ashift_n_lower): New. + 2003-01-24 Volker Reichelt <reichelt@igpm.rwth-aachen.de> * doc/bugreport.texi: Use @command instead of @code for commands. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index 966bf95..ec8a931 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -2597,6 +2597,27 @@ (clobber (scratch:QI))])] "") +;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B). + +(define_insn_and_split "*andsi3_ashift_n_lower" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:QI 2 "const_int_operand" "S,n")) + (match_operand:SI 3 "const_int_operand" "n,n"))) + (clobber (match_scratch:QI 4 "=X,&r"))] + "(TARGET_H8300H || TARGET_H8300S) + && INTVAL (operands[2]) <= 15 + && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 5) + (ashift:HI (match_dup 5) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 0) + (zero_extend:SI (match_dup 5)))] + "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));") + ;; Accept (A >> 30) & 2 and the like. (define_insn "*andsi3_lshiftrt_n_sb" |