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| author | Tamar Christina <tamar.christina@arm.com> | 2018-06-27 08:08:48 +0000 |
|---|---|---|
| committer | Tamar Christina <tnfchris@gcc.gnu.org> | 2018-06-27 08:08:48 +0000 |
| commit | d89fe63e58fb775fb4aa043e168b5025521d5a47 (patch) | |
| tree | 2665165a6b88000bc4e71ea1456a1b4a4d228d2d /gcc | |
| parent | 0e97b84bfc542a51c1db1dd4571faa827a02064a (diff) | |
| download | gcc-d89fe63e58fb775fb4aa043e168b5025521d5a47.zip gcc-d89fe63e58fb775fb4aa043e168b5025521d5a47.tar.gz gcc-d89fe63e58fb775fb4aa043e168b5025521d5a47.tar.bz2 | |
Add SIMD to REG pattern for movhf without armv8.2-a support for AArch64
This fixes a regression where we don't have an instruction for pre Armv8.2-a
to do a move of an fp16 value from a GP reg to a SIMD reg.
This patch adds that pattern to movhf_aarch64 using a dup and only selectes it
using a very low priority.
This fixes an ICE at -O0.
gcc/
2018-06-20 Tamar Christina <tamar.christina@arm.com>
PR target/85769
* config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern.
gcc/testsuite/
2018-06-20 Tamar Christina <tamar.christina@arm.com>
PR target/85769
* gcc.target/aarch64/f16_mov_immediate_3.c: New.
From-SVN: r262178
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c | 19 |
4 files changed, 35 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 773eeaa..194d2ee 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-06-27 Tamar Christina <tamar.christina@arm.com> + + PR target/85769 + * config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern. + 2018-06-27 Siddhesh Poyarekar <siddhesh@sourceware.org> * config/aarch64/aarch64.h (CALL_USE_REGISTERS): Fix obsolete diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 830f976..4ac6332 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1161,13 +1161,14 @@ ) (define_insn "*movhf_aarch64" - [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w ,w,m,r,m ,r") - (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r"))] + [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w , w,?r,w,w ,w ,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "Y ,?rY,?r, w,w,Ufc,Uvi,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ movi\\t%0.4h, #0 fmov\\t%h0, %w1 + dup\\t%w0.4h, %w1 umov\\t%w0, %1.h[0] mov\\t%0.h[0], %1.h[0] fmov\\t%h0, %1 @@ -1177,10 +1178,10 @@ ldrh\\t%w0, %1 strh\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "neon_move,f_mcr,neon_to_gp,neon_move,fconsts, \ + [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ neon_move,f_loads,f_stores,load_4,store_4,mov_reg") - (set_attr "simd" "yes,*,yes,yes,*,yes,*,*,*,*,*") - (set_attr "fp16" "*,yes,*,*,yes,*,*,*,*,*,*")] + (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") + (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 371c9f1..f20147a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-06-27 Tamar Christina <tamar.christina@arm.com> + + PR target/85769 + * gcc.target/aarch64/f16_mov_immediate_3.c: New. + 2018-06-26 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/builtins-1.c: Correct a comment. diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c new file mode 100644 index 0000000..6dc325b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +extern __fp16 foo (); + +__fp16 f4 () +{ + __fp16 a = 0; + __fp16 b = 1; + __fp16 c = 2; + __fp16 d = 4; + + __fp16 z = a + b; + z = z + c; + z = z - d; + return z; +} + +/* { dg-final { scan-assembler-times {dup\tv[0-9]+.4h, w[0-9]+} 1 } } */ |