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| author | Tamar Christina <tamar.christina@arm.com> | 2018-07-05 10:35:00 +0000 |
|---|---|---|
| committer | Tamar Christina <tnfchris@gcc.gnu.org> | 2018-07-05 10:35:00 +0000 |
| commit | d6e5a37a0402177713e9496f0d852e2e1147437f (patch) | |
| tree | d85c7d84a110e0a71b36508ccbabd5555582e968 /gcc | |
| parent | 89c52e5e2ca6e63b1dc0868893d05434d61a0c33 (diff) | |
| download | gcc-d6e5a37a0402177713e9496f0d852e2e1147437f.zip gcc-d6e5a37a0402177713e9496f0d852e2e1147437f.tar.gz gcc-d6e5a37a0402177713e9496f0d852e2e1147437f.tar.bz2 | |
Correct subreg no-op handling for big-endian vec_select.
gcc/
PR target/84711
* rtlanal.c (set_noop_p): Constrain on mode change,
include hard-reg-set.h
gcc/testuite/
PR target/84711
* gcc.dg/vect/pr84711.c: New.
From-SVN: r262435
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/rtlanal.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/pr84711.c | 12 |
4 files changed, 27 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f30e83d..046ca6e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2018-07-05 Tamar Christina <tamar.christina@arm.com> + PR target/84711 + * rtlanal.c (set_noop_p): Constrain on mode change, + include hard-reg-set.h + +2018-07-05 Tamar Christina <tamar.christina@arm.com> + * config/aarch64/aarch64.c (aarch64_expand_movmem): Fix mode size. 2018-07-05 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 8e8ee6e..9f84d7f 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -35,6 +35,7 @@ along with GCC; see the file COPYING3. If not see #include "recog.h" #include "addresses.h" #include "rtl-iter.h" +#include "hard-reg-set.h" /* Forward declarations */ static void set_of_1 (rtx, const_rtx, void *); @@ -1621,8 +1622,9 @@ set_noop_p (const_rtx set) if (maybe_ne (rtx_to_poly_int64 (XVECEXP (par, 0, i)), c0 + i)) return 0; return - simplify_subreg_regno (REGNO (src0), GET_MODE (src0), - offset, GET_MODE (dst)) == (int) REGNO (dst); + REG_CAN_CHANGE_MODE_P (REGNO (dst), GET_MODE (src0), GET_MODE (dst)) + && simplify_subreg_regno (REGNO (src0), GET_MODE (src0), + offset, GET_MODE (dst)) == (int) REGNO (dst); } return (REG_P (src) && REG_P (dst) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5ff92a4..cea62ec 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2018-07-05 Tamar Christina <tamar.christina@arm.com> + PR target/84711 + * gcc.dg/vect/pr84711.c: New. + +2018-07-05 Tamar Christina <tamar.christina@arm.com> + * gcc.target/aarch64/struct_cpy.c: New. 2018-07-05 Christophe Lyon <christophe.lyon@linaro.org> diff --git a/gcc/testsuite/gcc.dg/vect/pr84711.c b/gcc/testsuite/gcc.dg/vect/pr84711.c new file mode 100644 index 0000000..dbe61be --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr84711.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-options "-O2" } */ + +typedef int v4si + __attribute__ ((vector_size (16))); + +int fn1 (v4si p) +{ + return p[0]; +} + |