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| author | Uros Bizjak <uros@gcc.gnu.org> | 2016-07-13 00:06:51 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-07-13 00:06:51 +0200 |
| commit | d5caa0f89f44d3dbf4944258d4ce0c7f6559ce6c (patch) | |
| tree | 59d73f0f1c66ab8e9abee3cb71957371dfca0941 /gcc | |
| parent | 221b3e6c32a61f4491afc87ab5d926e1f6bcf464 (diff) | |
| download | gcc-d5caa0f89f44d3dbf4944258d4ce0c7f6559ce6c.zip gcc-d5caa0f89f44d3dbf4944258d4ce0c7f6559ce6c.tar.gz gcc-d5caa0f89f44d3dbf4944258d4ce0c7f6559ce6c.tar.bz2 | |
re PR tree-optimization/68961 (Test case gcc.target/powerpc/pr60203.c fails since r231674)
PR rtl-optimization/68961
* config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new
peephole variant. Use sse_reg_operand predicates.
From-SVN: r238268
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 20 |
2 files changed, 23 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6cb8da2..0b7518f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-07-13 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/68961 + * config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new + peephole variant. Use sse_reg_operand predicates. + 2016-07-12 Uros Bizjak <ubizjak@gmail.com> * config/i386/predicates.md (x86_64_immediate_operand) @@ -41,7 +47,7 @@ loops. 2016-07-12 Steven Bosscher <steven@gcc.gnu.org> - Richard Biener <rguenther@suse.de> + Richard Biener <rguenther@suse.de> PR tree-optimization/23286 PR tree-optimization/70159 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c1ea04f..6b898dc 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1169,10 +1169,10 @@ ;; Merge movsd/movhpd to movupd for TARGET_SSE_UNALIGNED_LOAD_OPTIMAL targets. (define_peephole2 - [(set (match_operand:V2DF 0 "register_operand") + [(set (match_operand:V2DF 0 "sse_reg_operand") (vec_concat:V2DF (match_operand:DF 1 "memory_operand") (match_operand:DF 4 "const0_operand"))) - (set (match_operand:V2DF 2 "register_operand") + (set (match_operand:V2DF 2 "sse_reg_operand") (vec_concat:V2DF (vec_select:DF (match_dup 2) (parallel [(const_int 0)])) (match_operand:DF 3 "memory_operand")))] @@ -1181,13 +1181,25 @@ [(set (match_dup 2) (match_dup 4))] "operands[4] = adjust_address (operands[1], V2DFmode, 0);") +(define_peephole2 + [(set (match_operand:DF 0 "sse_reg_operand") + (match_operand:DF 1 "memory_operand")) + (set (match_operand:V2DF 2 "sse_reg_operand") + (vec_concat:V2DF (match_operand:DF 4 "sse_reg_operand") + (match_operand:DF 3 "memory_operand")))] + "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL + && REGNO (operands[4]) == REGNO (operands[2]) + && ix86_operands_ok_for_move_multiple (operands, true, DFmode)" + [(set (match_dup 2) (match_dup 4))] + "operands[4] = adjust_address (operands[1], V2DFmode, 0);") + ;; Merge movlpd/movhpd to movupd for TARGET_SSE_UNALIGNED_STORE_OPTIMAL targets. (define_peephole2 [(set (match_operand:DF 0 "memory_operand") - (vec_select:DF (match_operand:V2DF 1 "register_operand") + (vec_select:DF (match_operand:V2DF 1 "sse_reg_operand") (parallel [(const_int 0)]))) (set (match_operand:DF 2 "memory_operand") - (vec_select:DF (match_operand:V2DF 3 "register_operand") + (vec_select:DF (match_operand:V2DF 3 "sse_reg_operand") (parallel [(const_int 1)])))] "TARGET_SSE2 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL && ix86_operands_ok_for_move_multiple (operands, false, DFmode)" |