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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-01-06 17:10:40 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2020-01-06 17:10:40 +0000 |
| commit | d54fc770768add469f646c20c0cab4e42510d895 (patch) | |
| tree | 8dd14ba4460d9410ead8f257806117cd4415b7a7 /gcc | |
| parent | 2b4f0b8951cbe95e5315428e7c6687307f236e6b (diff) | |
| download | gcc-d54fc770768add469f646c20c0cab4e42510d895.zip gcc-d54fc770768add469f646c20c0cab4e42510d895.tar.gz gcc-d54fc770768add469f646c20c0cab4e42510d895.tar.bz2 | |
Fix amdgcn issue with '0' constraints
2020-01-06 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
'0' matching inputs.
(subv64di3_exec): Likewise.
From-SVN: r279906
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 26 |
2 files changed, 19 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a3e5220..4ed0cd9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-01-06 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for + '0' matching inputs. + (subv64di3_exec): Likewise. + 2020-01-06 Bryan Stenson <bryan@siliconvortex.com> * config/mips/mips.c (vr4130_align_insns): Fix typo. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 9baef24..e301a43 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1292,10 +1292,10 @@ (set_attr "length" "8")]) (define_insn_and_split "subv64di3" - [(set (match_operand:V64DI 0 "register_operand" "= &v, &v") - (minus:V64DI - (match_operand:V64DI 1 "gcn_alu_operand" "vSvB0, v0") - (match_operand:V64DI 2 "gcn_alu_operand" " v0,vSvB0"))) + [(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v, &v") + (minus:V64DI + (match_operand:V64DI 1 "gcn_alu_operand" "vSvB,vSvB0, v, v0") + (match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vSvB0,vSvB"))) (clobber (reg:DI VCC_REG))] "" "#" @@ -1318,17 +1318,17 @@ DONE; } [(set_attr "type" "vmult") - (set_attr "length" "8,8")]) + (set_attr "length" "8")]) (define_insn_and_split "subv64di3_exec" - [(set (match_operand:V64DI 0 "register_operand" "= &v, &v") - (vec_merge:V64DI - (minus:V64DI - (match_operand:V64DI 1 "gcn_alu_operand" "vSvB0, v0") - (match_operand:V64DI 2 "gcn_alu_operand" " v0,vSvB0")) + [(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v, &v") + (vec_merge:V64DI + (minus:V64DI + (match_operand:V64DI 1 "gcn_alu_operand" "vSvB,vSvB0, v, v0") + (match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vSvB0,vSvB")) (match_operand:V64DI 3 "gcn_register_or_unspec_operand" - " U0, U0") - (match_operand:DI 4 "gcn_exec_reg_operand" " e, e"))) + " U0, U0, U0, U0") + (match_operand:DI 4 "gcn_exec_reg_operand" " e, e, e, e"))) (clobber (reg:DI VCC_REG))] "register_operand (operands[1], VOIDmode) || register_operand (operands[2], VOIDmode)" @@ -1357,7 +1357,7 @@ DONE; } [(set_attr "type" "vmult") - (set_attr "length" "8,8")]) + (set_attr "length" "8")]) (define_insn_and_split "addv64di3_dup" [(set (match_operand:V64DI 0 "register_operand" "= &v") |