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| author | Eric Botcazou <ebotcazou@adacore.com> | 2011-10-11 21:33:24 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2011-10-11 21:33:24 +0000 |
| commit | d0e2a1f832689d16161b2db826475ad6ef8a2950 (patch) | |
| tree | 3996c8d3b68795d47aacefa2268d08931471e74d /gcc | |
| parent | 60ca0fe6974aec0d7f9ec1defd30f214e768b3a3 (diff) | |
| download | gcc-d0e2a1f832689d16161b2db826475ad6ef8a2950.zip gcc-d0e2a1f832689d16161b2db826475ad6ef8a2950.tar.gz gcc-d0e2a1f832689d16161b2db826475ad6ef8a2950.tar.bz2 | |
re PR target/49965 (libgomp.c++/reduction-4.C and libgomp.c++/task-8.C FAIL on Solaris 11/SPARC)
PR target/49965
* config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code.
(mov<F:mode>cc): Likewise.
From-SVN: r179827
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 20 |
2 files changed, 16 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d3f6d2c..cd33d10 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-10-11 Eric Botcazou <ebotcazou@adacore.com> + + PR target/49965 + * config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code. + (mov<F:mode>cc): Likewise. + 2011-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * tree-ssa-address.c (copy_ref_info): Remove copy of TREE_THIS_NOTRAP. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index a6eba6c..24993fb 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2614,11 +2614,9 @@ (match_operand:I 3 "arith10_operand" "")))] "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)" { - enum rtx_code code = GET_CODE (operands[1]); rtx cc_reg; - if (GET_MODE (XEXP (operands[1], 0)) == DImode - && ! TARGET_ARCH64) + if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64) FAIL; if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) @@ -2629,12 +2627,14 @@ if (XEXP (operands[1], 1) == const0_rtx && GET_CODE (XEXP (operands[1], 0)) == REG && GET_MODE (XEXP (operands[1], 0)) == DImode - && v9_regcmp_p (code)) + && v9_regcmp_p (GET_CODE (operands[1]))) cc_reg = XEXP (operands[1], 0); else cc_reg = gen_compare_reg (operands[1]); - operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + operands[1] + = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg, + const0_rtx); }) (define_expand "mov<F:mode>cc" @@ -2644,11 +2644,9 @@ (match_operand:F 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" { - enum rtx_code code = GET_CODE (operands[1]); rtx cc_reg; - if (GET_MODE (XEXP (operands[1], 0)) == DImode - && ! TARGET_ARCH64) + if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64) FAIL; if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) @@ -2659,12 +2657,14 @@ if (XEXP (operands[1], 1) == const0_rtx && GET_CODE (XEXP (operands[1], 0)) == REG && GET_MODE (XEXP (operands[1], 0)) == DImode - && v9_regcmp_p (code)) + && v9_regcmp_p (GET_CODE (operands[1]))) cc_reg = XEXP (operands[1], 0); else cc_reg = gen_compare_reg (operands[1]); - operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + operands[1] + = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg, + const0_rtx); }) ;; Conditional move define_insns |