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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-09-17 17:01:10 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-17 17:01:10 +0000 |
| commit | d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5 (patch) | |
| tree | b8330840a9094d1f5621f3b10e6d1d611e2ad50c /gcc | |
| parent | f62281dc1b3d751977266d8c30b4488833fcb9dd (diff) | |
| download | gcc-d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5.zip gcc-d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5.tar.gz gcc-d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5.tar.bz2 | |
[arm][aarch64] Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE
Since no_insn patterns expand to no instructions, they shouldn't
count against the issue rate, just like USEs and CLOBBERs don't.
2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_sched_variable_issue): New
function.
(TARGET_SCHED_VARIABLE_ISSUE): New macro.
* config/arm/arm.c (arm_sched_variable_issue): New function.
(TARGET_SCHED_VARIABLE_ISSUE): New macro.
From-SVN: r275808
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 20 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 21 |
3 files changed, 49 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 26d0619..5a4fc2c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2019-09-17 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64.c (aarch64_sched_variable_issue): New + function. + (TARGET_SCHED_VARIABLE_ISSUE): New macro. + * config/arm/arm.c (arm_sched_variable_issue): New function. + (TARGET_SCHED_VARIABLE_ISSUE): New macro. + +2019-09-17 Richard Sandiford <richard.sandiford@arm.com> + * config/arm/types.md (no_reservation): New reservation. * config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle no_insn here. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ed04060..232317d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11804,6 +11804,23 @@ aarch64_sched_issue_rate (void) return aarch64_tune_params.issue_rate; } +/* Implement TARGET_SCHED_VARIABLE_ISSUE. */ +static int +aarch64_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) +{ + if (DEBUG_INSN_P (insn)) + return more; + + rtx_code code = GET_CODE (PATTERN (insn)); + if (code == USE || code == CLOBBER) + return more; + + if (get_attr_type (insn) == TYPE_NO_INSN) + return more; + + return more - 1; +} + static int aarch64_sched_first_cycle_multipass_dfa_lookahead (void) { @@ -20584,6 +20601,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate +#undef TARGET_SCHED_VARIABLE_ISSUE +#define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue + #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ aarch64_sched_first_cycle_multipass_dfa_lookahead diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b59778c..c9ab71e 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -257,6 +257,7 @@ static bool arm_sched_can_speculate_insn (rtx_insn *); static bool arm_macro_fusion_p (void); static bool arm_cannot_copy_insn_p (rtx_insn *); static int arm_issue_rate (void); +static int arm_sched_variable_issue (FILE *, int, rtx_insn *, int); static int arm_first_cycle_multipass_dfa_lookahead (void); static int arm_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *, int); static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; @@ -665,6 +666,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE arm_issue_rate +#undef TARGET_SCHED_VARIABLE_ISSUE +#define TARGET_SCHED_VARIABLE_ISSUE arm_sched_variable_issue + #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ arm_first_cycle_multipass_dfa_lookahead @@ -28495,6 +28499,23 @@ arm_issue_rate (void) return current_tune->issue_rate; } +/* Implement TARGET_SCHED_VARIABLE_ISSUE. */ +static int +arm_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) +{ + if (DEBUG_INSN_P (insn)) + return more; + + rtx_code code = GET_CODE (PATTERN (insn)); + if (code == USE || code == CLOBBER) + return more; + + if (get_attr_type (insn) == TYPE_NO_INSN) + return more; + + return more - 1; +} + /* Return how many instructions should scheduler lookahead to choose the best one. */ static int |