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| author | Richard Earnshaw <rearnsha@arm.com> | 2019-08-09 15:33:18 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2019-08-09 15:33:18 +0000 |
| commit | d092f6fce920a07d6dd319105ccf1cb9db05d029 (patch) | |
| tree | 92bda1b70fba7c036ba1306c83562b871aedfa56 /gcc | |
| parent | 9c4cb8615fc71a117c00844fd608ae6788acfd92 (diff) | |
| download | gcc-d092f6fce920a07d6dd319105ccf1cb9db05d029.zip gcc-d092f6fce920a07d6dd319105ccf1cb9db05d029.tar.gz gcc-d092f6fce920a07d6dd319105ccf1cb9db05d029.tar.bz2 | |
[arm] Recognize thumb2 16-bit variants of the add and compare instructions
The addsi3_compare_op[12] patterns currently only have constraints to
pick the 32-bit variants of the instructions. Although the assembler
may sometimes opportunistically match a 16-bit t2 instruction, there's
no real control over that within the compiler. Consequently we might
emit a 32-bit adds instruction with a 16-bit subs instruction would
serve equally well. We do, of course still have to be careful about
the small number of boundary cases by controlling the order quite
carefully.
This patch adds the constraints and templates to match the t2 16-bit
variants of these instructions. Now, for example, we can generate
subs r0, r0, #1 // 16-bit instruction
instead of
adds r0, r0, #1 // 32-bit instruction.
*confit/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants.
(addsi3_compare_op2): Likewise.
From-SVN: r274237
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 30 |
2 files changed, 27 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e9fd078..e19322b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-09 Richard Earnshaw <rearnsha@arm.com> + + *confit/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants. + (addsi3_compare_op2): Likewise. + 2019-08-09 Martin Liska <mliska@suse.cz> * alias.c (alias_ptr_types_compatible_p): Strengten diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ccc48a5..50e1b90 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -930,35 +930,49 @@ (define_insn "*addsi3_compare_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) (match_dup 1))) - (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ adds%?\\t%0, %1, %2 + adds%?\\t%0, %0, %2 + subs%?\\t%0, %1, #%n2 + subs%?\\t%0, %0, #%n2 + adds%?\\t%0, %1, %2 subs%?\\t%0, %1, #%n2 adds%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*,*") + (set_attr "length" "2,2,2,2,4,4,4") + (set_attr "type" + "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*addsi3_compare_op2" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) (match_dup 2))) - (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ adds%?\\t%0, %1, %2 + adds%?\\t%0, %0, %2 + subs%?\\t%0, %1, #%n2 + subs%?\\t%0, %0, #%n2 + adds%?\\t%0, %1, %2 subs%?\\t%0, %1, #%n2 adds%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*,*") + (set_attr "length" "2,2,2,2,4,4,4") + (set_attr "type" + "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*compare_addsi2_op0" |