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| author | James E Wilson <wilson@specifixinc.com> | 2004-09-06 23:55:44 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2004-09-06 16:55:44 -0700 |
| commit | cfd8e493bc2b7307c3d1b2d93ea08bd3c10c666c (patch) | |
| tree | fae3a9cfbcbd5a1f31c5976153f98e6ad0cfaf08 /gcc | |
| parent | 83f84d6c4e4f885d89afad11a01607e71d0a7d45 (diff) | |
| download | gcc-cfd8e493bc2b7307c3d1b2d93ea08bd3c10c666c.zip gcc-cfd8e493bc2b7307c3d1b2d93ea08bd3c10c666c.tar.gz gcc-cfd8e493bc2b7307c3d1b2d93ea08bd3c10c666c.tar.bz2 | |
Another MIPS vector cleanup patch, fix bad type attribute for FP zero moves.
* config/mips/mips.md (movsf_hardfloat, movdf_hardfloat_64bit,
movdf_hardfloat_32bit): Split fG into two alternatives.
(movv2sf_hardfloat_64bit): Split fYG into two alternatives.
From-SVN: r87132
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 32 |
2 files changed, 20 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 37260d7..62fb710 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2004-09-06 James E Wilson <wilson@specifixinc.com> + * config/mips/mips.md (movsf_hardfloat, movdf_hardfloat_64bit, + movdf_hardfloat_32bit): Split fG into two alternatives. + (movv2sf_hardfloat_64bit): Split fYG into two alternatives. + * emit-rtl.c (try_split): Check INSN_P before may_trap_p call. 2004-09-06 Eric Botcazou <ebotcazou@libertysurf.fr> diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 317e29b..9390ed0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3567,15 +3567,15 @@ beq\t%2,%.,1b\;\ }) (define_insn "*movsf_hardfloat" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m") - (match_operand:SF 1 "move_operand" "f,G,m,fG,*d,*f,*G*d,*m,*d"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") + (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))] "TARGET_HARD_FLOAT && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store") + [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") (set_attr "mode" "SF") - (set_attr "length" "4,4,*,*,4,4,4,*,*")]) + (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) (define_insn "*movsf_softfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m") @@ -3612,26 +3612,26 @@ beq\t%2,%.,1b\;\ }) (define_insn "*movdf_hardfloat_64bit" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m") - (match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") + (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store") + [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") (set_attr "mode" "DF") - (set_attr "length" "4,4,*,*,4,4,4,*,*")]) + (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) (define_insn "*movdf_hardfloat_32bit" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m") - (match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") + (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store") + [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") (set_attr "mode" "DF") - (set_attr "length" "4,8,*,*,8,8,8,*,*")]) + (set_attr "length" "4,8,*,*,*,8,8,8,*,*")]) (define_insn "*movdf_softfloat" [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f") @@ -3704,16 +3704,16 @@ beq\t%2,%.,1b\;\ }) (define_insn "movv2sf_hardfloat_64bit" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m") - (match_operand:V2SF 1 "move_operand" "f,YG,m,fYG,*d,*f,*d*YG,*m,*d"))] + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") + (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] "TARGET_PAIRED_SINGLE_FLOAT && TARGET_64BIT && (register_operand (operands[0], V2SFmode) || reg_or_0_operand (operands[1], V2SFmode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store") + [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") (set_attr "mode" "SF") - (set_attr "length" "4,4,*,*,4,4,4,*,*")]) + (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) ;; The HI and LO registers are not truly independent. If we move an mthi ;; instruction before an mflo instruction, it will make the result of the |