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| author | Andrew Stubbs <ams@codesourcery.com> | 2010-12-17 16:30:37 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2010-12-17 16:30:37 +0000 |
| commit | cfd688eafec70fd73d705a843c5eca3ca83372a9 (patch) | |
| tree | b68e256d26c859edff84d3da59f123bca4fb11df /gcc | |
| parent | eb67f09048dfc3181f6183a203971ef71cb39fb0 (diff) | |
| download | gcc-cfd688eafec70fd73d705a843c5eca3ca83372a9.zip gcc-cfd688eafec70fd73d705a843c5eca3ca83372a9.tar.gz gcc-cfd688eafec70fd73d705a843c5eca3ca83372a9.tar.bz2 | |
arm.md (maddhisi4, *maddhidi4): Use the canonical operand order for plus.
2010-12-17 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical
operand order for plus.
Drop redundant % from constraints.
From-SVN: r167991
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 14 |
2 files changed, 13 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 864cc63..66dfdd5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2010-12-17 Andrew Stubbs <ams@codesourcery.com> + + * config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical + operand order for plus. + Drop redundant % from constraints. + 2010-12-17 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * config/spu/t-spu-elf (LIB2FUNCS_EXCLUDE): Add _floattisf and diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 20431d3..dd7555b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1793,11 +1793,11 @@ (define_insn "maddhisi4" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (match_operand:SI 3 "s_register_operand" "r") - (mult:SI (sign_extend:SI - (match_operand:HI 1 "s_register_operand" "%r")) + (plus:SI (mult:SI (sign_extend:SI + (match_operand:HI 1 "s_register_operand" "r")) (sign_extend:SI - (match_operand:HI 2 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:SI 3 "s_register_operand" "r")))] "TARGET_DSP_MULTIPLY" "smlabb%?\\t%0, %1, %2, %3" [(set_attr "insn" "smlaxy") @@ -1807,11 +1807,11 @@ (define_insn "*maddhidi4" [(set (match_operand:DI 0 "s_register_operand" "=r") (plus:DI - (match_operand:DI 3 "s_register_operand" "0") (mult:DI (sign_extend:DI - (match_operand:HI 1 "s_register_operand" "%r")) + (match_operand:HI 1 "s_register_operand" "r")) (sign_extend:DI - (match_operand:HI 2 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:DI 3 "s_register_operand" "0")))] "TARGET_DSP_MULTIPLY" "smlalbb%?\\t%Q0, %R0, %1, %2" [(set_attr "insn" "smlalxy") |