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| author | Roger Sayle <roger@eyesopen.com> | 2004-07-31 00:03:38 +0000 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2004-07-31 00:03:38 +0000 |
| commit | cf14e33d62f736fd748bff4e0a0b9989199f0371 (patch) | |
| tree | d223b53dfc0576a64cc258d7e5cd4846a7109693 /gcc | |
| parent | 0534fa565255cf56d5771ea92522403947d4bbd4 (diff) | |
| download | gcc-cf14e33d62f736fd748bff4e0a0b9989199f0371.zip gcc-cf14e33d62f736fd748bff4e0a0b9989199f0371.tar.gz gcc-cf14e33d62f736fd748bff4e0a0b9989199f0371.tar.bz2 | |
i386.md: New peephole2's to convert imul by 3, 5 or 9 into the equivalent lea instruction.
* config/i386/i386.md: New peephole2's to convert imul by 3, 5 or
9 into the equivalent lea instruction.
Co-Authored-By: Richard Henderson <rth@redhat.com>
From-SVN: r85366
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 63 |
2 files changed, 69 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e46f01b..9535b8c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-07-30 Roger Sayle <roger@eyesopen.com> + Richard Henderson <rth@redhat.com> + + * config/i386/i386.md: New peephole2's to convert imul by 3, 5 or + 9 into the equivalent lea instruction. + 2004-07-30 Richard Henderson <rth@redhat.com> * gimplify.c (gimplify_expr) <case CONST_DECL>: Don't replace diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9421cc7..12c051e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -19326,6 +19326,69 @@ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") +;; Convert imul by three, five and nine into lea +(define_peephole2 + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (mult:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9" + [(set (match_dup 0) + (plus:SI (mult:SI (match_dup 1) (match_dup 2)) + (match_dup 1)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (mult:SI (match_operand:SI 1 "nonimmediate_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "!optimize_size + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) + (plus:SI (mult:SI (match_dup 0) (match_dup 2)) + (match_dup 0)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_64BIT + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) + (plus:DI (mult:DI (match_dup 1) (match_dup 2)) + (match_dup 1)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (match_operand:DI 1 "nonimmediate_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_64BIT + && !optimize_size + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) + (plus:DI (mult:DI (match_dup 0) (match_dup 2)) + (match_dup 0)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + ;; Imul $32bit_imm, mem, reg is vector decoded, while ;; imul $32bit_imm, reg, reg is direct decoded. (define_peephole2 |