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| author | Kito Cheng <kito.cheng@gmail.com> | 2018-02-26 07:01:08 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-02-26 07:01:08 +0000 |
| commit | cc9b241b51c485a746284bf583a99ec68008fc31 (patch) | |
| tree | 9a9264da79b27b19a6596542602fdf9e31b41816 /gcc | |
| parent | 7f3101c0a87f5be1dcf1811e8e54fb4b32cd2397 (diff) | |
| download | gcc-cc9b241b51c485a746284bf583a99ec68008fc31.zip gcc-cc9b241b51c485a746284bf583a99ec68008fc31.tar.gz gcc-cc9b241b51c485a746284bf583a99ec68008fc31.tar.bz2 | |
[NDS32] Do not use multiple load/store instructions for volatile memory access.
gcc/
* config/nds32/nds32-multiple.md(load_multiple): Disallow
volatile memory.
(store_multiple): Ditto.
Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r257983
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32-multiple.md | 8 |
2 files changed, 14 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f1920f..bc2bde0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,7 +1,14 @@ 2018-02-26 Kito Cheng <kito.cheng@gmail.com> + Chung-Ju Wu <jasonwucj@gmail.com> + + * config/nds32/nds32-multiple.md (load_multiple): Disallow + volatile memory. + (store_multiple): Ditto. + +2018-02-26 Kito Cheng <kito.cheng@gmail.com> * config.gcc: Add --with-cpu support for nds32 target. - * config/nds32/nds32-opts.h(nds32_cpu_type): New. + * config/nds32/nds32-opts.h (nds32_cpu_type): New. * config/nds32/nds32.opt: Add -mcpu= option. 2018-02-25 Segher Boessenkool <segher@kernel.crashing.org> diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md index 581a74f..238e8c2 100644 --- a/gcc/config/nds32/nds32-multiple.md +++ b/gcc/config/nds32/nds32-multiple.md @@ -54,12 +54,14 @@ (based on this nds32-multiple.md design). 4. operands[0] must be register for sure. 5. operands[1] must be memory for sure. - 6. Do not cross $r15 register because it is not allocatable. */ + 6. operands[1] is not volatile memory access. + 7. Do not cross $r15 register because it is not allocatable. */ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > maximum || INTVAL (operands[2]) < 2 || GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != MEM + || MEM_VOLATILE_P (operands[1]) || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM) FAIL; @@ -236,12 +238,14 @@ (based on this nds32-multiple.md design). 4. operands[0] must be memory for sure. 5. operands[1] must be register for sure. - 6. Do not cross $r15 register because it is not allocatable. */ + 6. operands[0] is not volatile memory access. + 7. Do not cross $r15 register because it is not allocatable. */ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > maximum || INTVAL (operands[2]) < 2 || GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != REG + || MEM_VOLATILE_P (operands[0]) || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM) FAIL; |