diff options
| author | Paul Brook <paul@codesourcery.com> | 2004-04-08 19:02:24 +0000 |
|---|---|---|
| committer | Paul Brook <pbrook@gcc.gnu.org> | 2004-04-08 19:02:24 +0000 |
| commit | cc81dde821dd144faa36924fe5c5febd54c64649 (patch) | |
| tree | 704ed31b068d4210b5cc856d520ea67c970aa629 /gcc | |
| parent | d4453b7ac50559127a64a0ee001918a8456cba54 (diff) | |
| download | gcc-cc81dde821dd144faa36924fe5c5febd54c64649.zip gcc-cc81dde821dd144faa36924fe5c5febd54c64649.tar.gz gcc-cc81dde821dd144faa36924fe5c5febd54c64649.tar.bz2 | |
arm.h (CLASS_LIKELY_SPILLED_P): Define.
* arm.h (CLASS_LIKELY_SPILLED_P): Define.
testsuite
* gcc.dg/spill-1.c: New test.
From-SVN: r80519
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 7 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/spill-1.c | 15 |
4 files changed, 30 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 231b9e7..dfda231 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2004-04-08 Paul Brook <paul@codesourcery.com> + * arm.h (CLASS_LIKELY_SPILLED_P): Define. + +2004-04-08 Paul Brook <paul@codesourcery.com> + * explow.c (promote_mode): Use PROMOTE_FUNCTION_MODE instead of PROMOTE_FOR_CALL_ONLY. * config/arm/arm-protos.h (arm_function_value): Declare. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 0c3f2fe..8af53df 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1378,6 +1378,13 @@ enum reg_class || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ : 0) +/* We need to define this for LO_REGS on thumb. Otherwise we can end up + using r0-r4 for function arguments, r7 for the stack frame and don't + have enough left over to do doubleword arithmetic. */ +#define CLASS_LIKELY_SPILLED_P(CLASS) \ + ((TARGET_THUMB && (CLASS) == LO_REGS) \ + || (CLASS) == CC_REG) + /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d0aa28f..d714f2e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2004-04-08 Paul Brook <paul@codesourcery.com> + + * gcc.dg/spill-1.c: New test. + 2004-04-08 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * gcc.dg/torture/builtin-ctype-2.c: New test. diff --git a/gcc/testsuite/gcc.dg/spill-1.c b/gcc/testsuite/gcc.dg/spill-1.c new file mode 100644 index 0000000..b85942e --- /dev/null +++ b/gcc/testsuite/gcc.dg/spill-1.c @@ -0,0 +1,15 @@ +/* This caused an ICE during register spilling when targeting thumb. + There are 8 registers available for arithmetic operations (r0-r7) + r7 is the frame pointer, and r0-r3 are used to pass arguments. + Combine was extending the lives of the arguments (in r0-r3) up until the + call to z. This leaves only 3 regs free which isn't enough to preform the + doubleword addition. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-omit-frame-pointer" } */ +void z(int); +int foo(int a, int b, int c, int d, long long *q) +{ + *q=*q+1; + z (a+b+c+d); +} + |