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| author | Jim Wilson <wilson@cygnus.com> | 1998-10-23 14:00:08 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1998-10-23 07:00:08 -0700 |
| commit | ca3bf2b5db619ff2f19ac253c05db30c9b84bf56 (patch) | |
| tree | 40d3edf44a9a53b12249769fc1539abebd49ef64 /gcc | |
| parent | e1ba7da73f740ffe54029e33b71f649cb299959d (diff) | |
| download | gcc-ca3bf2b5db619ff2f19ac253c05db30c9b84bf56.zip gcc-ca3bf2b5db619ff2f19ac253c05db30c9b84bf56.tar.gz gcc-ca3bf2b5db619ff2f19ac253c05db30c9b84bf56.tar.bz2 | |
Fix m32r build failure, (SUBREG (MEM)) problem from Joern's reload patches.
* m32r/m32r.c (gen_split_move_double): Call alter_subreg. Delete
subreg support.
From-SVN: r23256
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/m32r/m32r.c | 25 |
2 files changed, 23 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 554dab1..eba3f14 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Fri Oct 23 13:55:48 1998 Jim Wilson <wilson@cygnus.com> + + * m32r/m32r.c (gen_split_move_double): Call alter_subreg. Delete + subreg support. + Fri Oct 23 16:19:24 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * mips.h (EXTRA_SPECS): Add missing initializers. diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index 41f7ce3..3474ad6 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -1123,16 +1123,29 @@ gen_split_move_double (operands) rtx src = operands[1]; rtx val; + /* We might have (SUBREG (MEM)) here, so just get rid of the + subregs to make this code simpler. It is safe to call + alter_subreg any time after reload. */ + if (GET_CODE (dest) == SUBREG) + dest = alter_subreg (dest); + if (GET_CODE (src) == SUBREG) + src = alter_subreg (src); + start_sequence (); - if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG) + if (GET_CODE (dest) == REG) { + int dregno = REGNO (dest); + /* reg = reg */ - if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG) + if (GET_CODE (src) == REG) { + int sregno = REGNO (src); + + int reverse = (dregno == sregno + 1); + /* We normally copy the low-numbered register first. However, if the first register operand 0 is the same as the second register of operand 1, we must copy in the opposite order. */ - int reverse = (REGNO (operands[0]) == REGNO (operands[1]) + 1); emit_insn (gen_rtx_SET (VOIDmode, operand_subword (dest, reverse, TRUE, mode), operand_subword (src, reverse, TRUE, mode))); @@ -1162,8 +1175,7 @@ gen_split_move_double (operands) /* If the high-address word is used in the address, we must load it last. Otherwise, load it first. */ rtx addr = XEXP (src, 0); - int reverse = (refers_to_regno_p (REGNO (dest), REGNO (dest)+1, - addr, 0) != 0); + int reverse = (refers_to_regno_p (dregno, dregno+1, addr, 0) != 0); /* We used to optimize loads from single registers as @@ -1205,8 +1217,7 @@ gen_split_move_double (operands) st r1,r3; st r2,+r3; addi r3,-4 which saves 2 bytes and doesn't force longword alignment. */ - else if (GET_CODE (dest) == MEM - && (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)) + else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG) { rtx addr = XEXP (dest, 0); |