diff options
| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2013-08-01 15:00:41 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2013-08-01 15:00:41 +0000 |
| commit | c743b246435838c846861d22430fea543a4eed7d (patch) | |
| tree | f4d8e4dc4834802f692844486af961571394666a /gcc | |
| parent | c0c123ef5222b0e12a5984640f0dd4db4ada569c (diff) | |
| download | gcc-c743b246435838c846861d22430fea543a4eed7d.zip gcc-c743b246435838c846861d22430fea543a4eed7d.tar.gz gcc-c743b246435838c846861d22430fea543a4eed7d.tar.bz2 | |
arm.md (peepholes for eq (reg1) (reg2/imm)): Generate canonical plus rtx with negated immediate instead of minus where...
[gcc]
2013-08-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)):
Generate canonical plus rtx with negated immediate instead of minus
where appropriate.
* config/arm/arm.c (thumb2_reorg): Handle ADCS <Rd>, <Rn> case.
[gcc/testsuite]
* gcc.target/arm/pr46972-2.c: New test.
From-SVN: r201411
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 10 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 16 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr46975-2.c | 10 |
5 files changed, 42 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19959d6..5480545 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-08-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)): + Generate canonical plus rtx with negated immediate instead of minus + where appropriate. + * config/arm/arm.c (thumb2_reorg): Handle ADCS <Rd>, <Rn> case. + 2013-08-01 Jan Hubicka <jh@suse.cz> * cgraph.c (cgraph_release_function_body): Use used_as_abstract_origin. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 0ee4d91..8c1dce9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -14360,6 +14360,16 @@ thumb2_reorg (void) && IN_RANGE (INTVAL (op1), -7, 7)) action = CONV; } + /* ADCS <Rd>, <Rn> */ + else if (GET_CODE (XEXP (src, 0)) == PLUS + && rtx_equal_p (XEXP (XEXP (src, 0), 0), dst) + && low_register_operand (XEXP (XEXP (src, 0), 1), + SImode) + && COMPARISON_P (op1) + && cc_register (XEXP (op1, 0), VOIDmode) + && maybe_get_arm_condition_code (op1) == ARM_CS + && XEXP (op1, 1) == const0_rtx) + action = CONV; break; case MINUS: diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3cdfc8e..322aa20 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10094,7 +10094,7 @@ (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] ) -;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 +;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 and optimising for speed. ;; sub Rd, Reg1, reg2 ;; clz Rd, Rd ;; lsr Rd, Rd, #5 @@ -10106,14 +10106,15 @@ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1)))] - "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" + "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM) + && !(TARGET_THUMB2 && optimize_insn_for_size_p ())" [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (clz:SI (match_dup 0))) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] ) -;; Rd = (eq (reg1) (reg2/imm)) // ! ARMv5 +;; Rd = (eq (reg1) (reg2)) // ! ARMv5 or optimising for size. ;; sub T1, Reg1, reg2 ;; negs Rd, T1 ;; adc Rd, Rd, T1 @@ -10127,7 +10128,7 @@ (set (match_dup 0) (const_int 1))) (match_scratch:SI 3 "r")] "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" - [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) + [(set (match_dup 3) (match_dup 4)) (parallel [(set (reg:CC CC_REGNUM) (compare:CC (const_int 0) (match_dup 3))) @@ -10135,7 +10136,12 @@ (set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 3)) (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] -) + " + if (CONST_INT_P (operands[2])) + operands[4] = plus_constant (SImode, operands[1], -INTVAL (operands[2])); + else + operands[4] = gen_rtx_MINUS (SImode, operands[1], operands[2]); + ") (define_insn "*cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3983844..61b8ee6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-08-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/arm/pr46972-2.c: New test. + 2013-08-01 Vidya Praveen <vidyapraveen@arm.com> * gcc.dg/vect/vect-iv-5.c: Make xfail conditional with !arm_neon_ok. diff --git a/gcc/testsuite/gcc.target/arm/pr46975-2.c b/gcc/testsuite/gcc.target/arm/pr46975-2.c new file mode 100644 index 0000000..f4017e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr46975-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "sub" } } */ +/* { dg-final { scan-assembler "clz" } } */ +/* { dg-final { scan-assembler "lsr.*#5" } } */ + +int foo (int s) +{ + return s == 1; +} |