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authorRichard Henderson <rth@redhat.com>2002-01-09 03:02:07 -0800
committerRichard Henderson <rth@gcc.gnu.org>2002-01-09 03:02:07 -0800
commitc73a5e94e8ab35d592b5335aabbb27433be082d9 (patch)
treed9eaa3c02200ecda1b4ca6631f63e1451c9f27c2 /gcc
parent9dee8c457021445d58dc2d4769a48c7b9f9a5879 (diff)
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m32r.c (move_src_operand): Fix 32-bit int test.
* config/m32r/m32r.c (move_src_operand): Fix 32-bit int test. * config/m32r/m32r.md (and ior xor splitters): Swap operands to match insn patterns. From-SVN: r48679
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/m32r/m32r.c8
-rw-r--r--gcc/config/m32r/m32r.md6
3 files changed, 16 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7df79a9..65dc90f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
2002-01-09 Richard Henderson <rth@redhat.com>
+ * config/m32r/m32r.c (move_src_operand): Fix 32-bit int test.
+ * config/m32r/m32r.md (and ior xor splitters): Swap operands
+ to match insn patterns.
+
+2002-01-09 Richard Henderson <rth@redhat.com>
+
* regrename.c (find_oldest_value_reg): Use gen_rtx_raw_REG.
(copyprop_hardreg_forward_1): Likewise.
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index a3692c9..9ae218e 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -793,7 +793,13 @@ move_src_operand (op, mode)
loadable with one insn, and split the rest into two. The instances
where this would help should be rare and the current way is
simpler. */
- return UINT32_P (INTVAL (op));
+ if (HOST_BITS_PER_WIDE_INT > 32)
+ {
+ HOST_WIDE_INT rest = INTVAL (op) >> 31;
+ return (rest == 0 || rest == -1);
+ }
+ else
+ return 1;
case LABEL_REF :
return TARGET_ADDR24;
case CONST_DOUBLE :
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 2d10057..a8e28db 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -1032,7 +1032,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "iorsi3"
@@ -1064,7 +1064,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "xorsi3"
@@ -1096,7 +1096,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "negsi2"