i386.md (sse_andti3, [...]): Add SSE2 versions; add missing '%' in constraints.

	* i386.md (sse_andti3, sse_nandti_3, sse_xorti3): Add SSE2 versions;
	add missing '%' in constraints.

From-SVN: r40127

6 files changed, 205 insertions, 37 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 79ee955..89f7af6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Wed Feb 28 18:47:37 CET 2001  Jan Hubicka  <jh@suse.cz>
+
+	* i386.md (sse_andti3, sse_nandti_3, sse_xorti3): Add SSE2 versions;
+	add missing '%' in constraints.
+
 Wed Feb 28 17:24:24 CET 2001  Jan Hubicka  <jh@suse.cz>
 
 	* c-common.c (build_common_tree_nodes): Build intTI_type_nodes
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 25a283f..0e65701 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -13917,38 +13917,182 @@
 ;; into DImode subregs of SSE registers, and them together, and move out
 ;; of DImode subregs again!
 
+(define_insn "*sse_andti3_df_1"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+  "TARGET_SSE2"
+  "andpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_andti3_df_2"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+  "TARGET_SSE2"
+  "andpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_andti3_sf_1"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
+  "TARGET_SSE"
+  "andps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_andti3_sf_2"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE"
+  "andps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
 (define_insn "sse_andti3"
   [(set (match_operand:TI 0 "register_operand" "=x")
-        (and:TI (match_operand:TI 1 "register_operand" "0")
+        (and:TI (match_operand:TI 1 "register_operand" "%0")
 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE"
+  "TARGET_SSE && !TARGET_SSE2"
   "andps\\t{%2, %0|%0, %2}"
   [(set_attr "type" "sse")])
 
+(define_insn "*sse_andti3_sse2"
+  [(set (match_operand:TI 0 "register_operand" "=x")
+        (and:TI (match_operand:TI 1 "register_operand" "%0")
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE2"
+  "pand\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_nandti3_df"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
+		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+  "TARGET_SSE2"
+  "andnpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_nandti3_sf"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE"
+  "andnps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
 (define_insn "sse_nandti3"
   [(set (match_operand:TI 0 "register_operand" "=x")
         (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE"
+  "TARGET_SSE && !TARGET_SSE2"
   "andnps\\t{%2, %0|%0, %2}"
   [(set_attr "type" "sse")])
 
+(define_insn "*sse_nandti3_sse2"
+  [(set (match_operand:TI 0 "register_operand" "=x")
+        (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE2"
+  "pnand\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_iorti3_df_1"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+  "TARGET_SSE2"
+  "orpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_iorti3_df_2"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+  "TARGET_SSE2"
+  "orpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_iorti3_sf_1"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
+  "TARGET_SSE"
+  "orps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_iorti3_sf_2"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE"
+  "orps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
 (define_insn "sse_iorti3"
   [(set (match_operand:TI 0 "register_operand" "=x")
-        (ior:TI (match_operand:TI 1 "register_operand" "0")
+        (ior:TI (match_operand:TI 1 "register_operand" "%0")
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE && !TARGET_SSE2"
+  "orps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_iorti3_sse2"
+  [(set (match_operand:TI 0 "register_operand" "=x")
+        (ior:TI (match_operand:TI 1 "register_operand" "%0")
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE2"
+  "por\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_xorti3_df_1"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
+  "TARGET_SSE2"
+  "xorpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_xorti3_df_2"
+  [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
+        (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
+		(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
+  "TARGET_SSE2"
+  "xorpd\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_xorti3_sf_1"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
+		(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
+  "TARGET_SSE"
+  "xorps\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
+(define_insn "*sse_xorti3_sf_2"
+  [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
+        (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
   "TARGET_SSE"
-  "iorps\\t{%2, %0|%0, %2}"
+  "xorps\\t{%2, %0|%0, %2}"
   [(set_attr "type" "sse")])
 
 (define_insn "sse_xorti3"
   [(set (match_operand:TI 0 "register_operand" "=x")
-        (xor:TI (match_operand:TI 1 "register_operand" "0")
+        (xor:TI (match_operand:TI 1 "register_operand" "%0")
 		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE"
+  "TARGET_SSE && !TARGET_SSE2"
   "xorps\\t{%2, %0|%0, %2}"
   [(set_attr "type" "sse")])
 
+(define_insn "*sse_xorti3_sse2"
+  [(set (match_operand:TI 0 "register_operand" "=x")
+        (xor:TI (match_operand:TI 1 "register_operand" "%0")
+		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
+  "TARGET_SSE2"
+  "pxor\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sse")])
+
 ;; Use xor, but don't show input operands so they aren't live before
 ;; this insn.
 (define_insn "sse_clrti"
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index ce3efaf..7bf8594 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -1732,6 +1732,9 @@ dwarf2out_frame_debug (insn)
 
   if (insn == NULL_RTX)
     {
+      rtx insn;
+      int n_alternate_entry_points;
+
       /* Set up state for generating call frame debug info.  */
       lookup_cfa (&cfa);
       if (cfa.reg != (unsigned long) DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM))
@@ -1740,6 +1743,39 @@ dwarf2out_frame_debug (insn)
       cfa_store = cfa;
       cfa_temp.reg = -1;
       cfa_temp.offset = 0;
+
+      n_alternate_entry_points = 0;
+      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+	if (GET_CODE (insn) == CODE_LABEL && LABEL_ALTERNATE_NAME (insn))
+	  n_alternate_entry_points ++;
+
+      /* For each alternate entry point amit an store_state command.  We will pop
+	 the state once we will reach it.  */
+      while (n_alternate_entry_points--)
+	{
+	  register dw_cfi_ref xcfi;
+
+	  /* Set the location counter to the new label.  */
+	  xcfi = new_cfi ();
+	  xcfi->dw_cfi_opc = DW_CFA_remember_state;
+	  add_fde_cfi (NULL, xcfi);
+	}
+      return;
+    }
+  /* An alternate entry point.  Pop the state we pushed during initialization
+     and re-initialize our tables.  */
+  if (GET_CODE (insn) == CODE_LABEL && LABEL_ALTERNATE_NAME (insn))
+    {
+      register dw_cfi_ref xcfi;
+      label = dwarf2out_cfi_label ();
+
+      /* On entry, the Canonical Frame Address is at SP.  */
+      dwarf2out_def_cfa (label, STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
+
+      /* Restore the frame state we had right before entering function.  */
+      xcfi = new_cfi ();
+      xcfi->dw_cfi_opc = DW_CFA_restore_state;
+      add_fde_cfi (label, xcfi);
       return;
     }
 
diff --git a/gcc/final.c b/gcc/final.c
index 70d6add..7a8e714 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -2332,6 +2332,12 @@ final_scan_insn (insn, file, optimize, prescan, nopeepholes)
       break;
 
     case CODE_LABEL:
+#if defined (DWARF2_UNWIND_INFO)
+      /* If we push arguments, we need to check all insns for stack
+	 adjustments.  */
+      if (dwarf2out_do_frame ())
+	dwarf2out_frame_debug (insn);
+#endif
       /* The target port might emit labels in the output function for
 	 some insn, e.g. sh.c output_branchy_insn.  */
       if (CODE_LABEL_NUMBER (insn) <= max_labelno)
diff --git a/gcc/jump.c b/gcc/jump.c
index bda1c6b..544c16b 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -1874,35 +1874,6 @@ reversed_comparison_code (comparison, insn)
 					 XEXP (comparison, 1), insn);
 }
 
-/* Given a comparison, COMPARISON, inside a conditional jump insn, INSN,
-   return non-zero if it is safe to reverse this comparison.  It is if our
-   floating-point is not IEEE, if this is an NE or EQ comparison, or if
-   this is known to be an integer comparison.  
- 
-   Use of this function is depreached and you should use
-   REVERSED_COMPARISON_CODE bits instead.
- */
-
-int
-can_reverse_comparison_p (comparison, insn)
-     rtx comparison;
-     rtx insn;
-{
-  enum rtx_code code;
-
-  /* If this is not actually a comparison, we can't reverse it.  */
-  if (GET_RTX_CLASS (GET_CODE (comparison)) != '<')
-    return 0;
-
-  code = reversed_comparison_code (comparison, insn);
-  if (code == UNKNOWN)
-    return 0;
-
-  /* The code will follow can_reverse_comparison_p with reverse_condition,
-     so see if it will get proper result.  */
-  return (code == reverse_condition (GET_CODE (comparison)));
-}
-
 /* Given an rtx-code for a comparison, return the code for the negated
    comparison.  If no such code exists, return UNKNOWN.
 
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 924c50b..b316178 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -3489,8 +3489,14 @@ rest_of_compilation (decl)
     }
 
   /* If optimizing, then go ahead and split insns now since we are about
-     to recompute flow information anyway.  */
+     to recompute flow information anyway.  Since we can't split insns after
+     reload, do the splitting unconditionally here to avoid gcc from losing
+     REG_DEAD notes.  */
+#ifdef STACK_REGS
+  if (1)
+#else
   if (optimize > 0)
+#endif
     {
       int old_labelnum = max_label_num ();