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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-11-03 12:08:26 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2016-11-03 12:08:26 +0000 |
| commit | c096a329934deeb33448adae4f286813895c8101 (patch) | |
| tree | b7b35835e3fa2991f5d8770e247d1bf2d30b9091 /gcc | |
| parent | db64c64e7d150e43721ad00e725d7cb2ccecc7f8 (diff) | |
| download | gcc-c096a329934deeb33448adae4f286813895c8101.zip gcc-c096a329934deeb33448adae4f286813895c8101.tar.gz gcc-c096a329934deeb33448adae4f286813895c8101.tar.bz2 | |
[rtlanal] Fix WORD_REGISTER_OPERATIONS condition in nonzero_bits
* rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition.
Move comments into more natural position.
From-SVN: r241815
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/rtlanal.c | 14 |
2 files changed, 12 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f0eb5f..22b16c5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-11-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition. + Move comments into more natural position. + 2016-11-03 Vineet Gupta <vgupta@synopsys.com> * config/arc/arc.h (SIZE_TYPE): Define as unsigned int. diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 508c663..4ebb314 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4568,18 +4568,18 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, known_x, known_mode, known_ret); #ifdef LOAD_EXTEND_OP - /* If this is a typical RISC machine, we only have to worry - about the way loads are extended. */ - if (WORD_REGISTER_OPERATIONS - && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + /* On many CISC machines, accessing an object in a wider mode + causes the high-order bits to become undefined. So they are + not known to be zero. */ + if (!WORD_REGISTER_OPERATIONS + /* If this is a typical RISC machine, we only have to worry + about the way loads are extended. */ + || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) #endif { - /* On many CISC machines, accessing an object in a wider mode - causes the high-order bits to become undefined. So they are - not known to be zero. */ if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) nonzero |= (GET_MODE_MASK (GET_MODE (x)) |