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| author | Eric Botcazou <ebotcazou@adacore.com> | 2018-01-31 15:01:40 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2018-01-31 15:01:40 +0000 |
| commit | bcec133fa9b1f65adcb68dbf7c9794019ddb66f3 (patch) | |
| tree | 14576ed965c324b15e9dd502eac9e09e6adcae37 /gcc | |
| parent | cb6a6b25e409efd06ad7ffb87cf73bbe243d704a (diff) | |
| download | gcc-bcec133fa9b1f65adcb68dbf7c9794019ddb66f3.zip gcc-bcec133fa9b1f65adcb68dbf7c9794019ddb66f3.tar.gz gcc-bcec133fa9b1f65adcb68dbf7c9794019ddb66f3.tar.bz2 | |
re PR rtl-optimization/84071 (wrong elimination of zero-extension after sign-extended load)
PR rtl-optimization/84071
* doc/tm.texi.in (WORD_REGISTER_OPERATIONS): Add explicit case.
* doc/tm.texi: Regenerate.
From-SVN: r257237
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/doc/tm.texi | 8 | ||||
| -rw-r--r-- | gcc/doc/tm.texi.in | 8 |
3 files changed, 18 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1e0891..40d570b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-01-31 Eric Botcazou <ebotcazou@adacore.com> + + PR rtl-optimization/84071 + * doc/tm.texi.in (WORD_REGISTER_OPERATIONS): Add explicit case. + * doc/tm.texi: Regenerate. + 2018-01-31 Richard Biener <rguenther@suse.de> PR tree-optimization/84132 diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 2f317b5..ddf48cb4 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -10766,8 +10766,12 @@ five otherwise. This is best for most machines. @defmac WORD_REGISTER_OPERATIONS Define this macro to 1 if operations between registers with integral mode -smaller than a word are always performed on the entire register. -Most RISC machines have this property and most CISC machines do not. +smaller than a word are always performed on the entire register. To be +more explicit, if you start with a pair of @code{word_mode} registers with +known values and you do a subword, for example @code{QImode}, addition on +the low part of the registers, then the compiler may consider that the +result has a known value in @code{word_mode} too if the macro is defined +to 1. Most RISC machines have this property and most CISC machines do not. @end defmac @deftypefn {Target Hook} {unsigned int} TARGET_MIN_ARITHMETIC_PRECISION (void) diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 2a42038..0aab45f 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -7376,8 +7376,12 @@ is in effect. @defmac WORD_REGISTER_OPERATIONS Define this macro to 1 if operations between registers with integral mode -smaller than a word are always performed on the entire register. -Most RISC machines have this property and most CISC machines do not. +smaller than a word are always performed on the entire register. To be +more explicit, if you start with a pair of @code{word_mode} registers with +known values and you do a subword, for example @code{QImode}, addition on +the low part of the registers, then the compiler may consider that the +result has a known value in @code{word_mode} too if the macro is defined +to 1. Most RISC machines have this property and most CISC machines do not. @end defmac @hook TARGET_MIN_ARITHMETIC_PRECISION |