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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2016-11-07 21:54:42 +0100 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2016-11-07 21:54:42 +0100 |
| commit | b7fa8414c43a7b5f2971753473f550af94481ff3 (patch) | |
| tree | 48bef69e7dcc992247d74c22ce95378ddfe0acd0 /gcc | |
| parent | fda2d61208385823f6b75f637eed60a9e77256c1 (diff) | |
| download | gcc-b7fa8414c43a7b5f2971753473f550af94481ff3.zip gcc-b7fa8414c43a7b5f2971753473f550af94481ff3.tar.gz gcc-b7fa8414c43a7b5f2971753473f550af94481ff3.tar.bz2 | |
rs6000: Do swdiv at expand time
We transform floating point divide instructions to a faster series of
simple instructions, "swdiv". Currently we do not do that until the
first splitter pass, which is much too late for most optimisations
that can happen on those new instructions, e.g. the constant loads
are not CSEd inside an unrolled loop. This patch changes things so
those divide instructions are expanded during expand already.
* config/rs6000/rs6000.md (div<mode>3): Expand using rs6000_emit_swdiv
if appropriate.
* config/rs6000/vector.md (div<mode>3): Ditto.
From-SVN: r241935
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/vector.md | 10 |
3 files changed, 24 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ce1f8e3d..8e6646b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-07 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (div<mode>3): Expand using rs6000_emit_swdiv + if appropriate. + * config/rs6000/vector.md (div<mode>3): Ditto. + 2016-11-06 David Edelsohn <dje.gcc@gmail.com> * configure.ac (.hidden): Change to conftest_s string. Provide string diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 43270f8..d409549 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4460,7 +4460,15 @@ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") (match_operand:SFDF 2 "gpc_reg_operand" "")))] "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" - "") +{ + if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) + && can_create_pseudo_p () && flag_finite_math_only + && !flag_trapping_math && flag_reciprocal_math) + { + rs6000_emit_swdiv (operands[0], operands[1], operands[2], true); + DONE; + } +}) (define_insn "*div<mode>3_fpr" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 7240345..05f3bdb 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -248,7 +248,15 @@ (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") (match_operand:VEC_F 2 "vfloat_operand" "")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" - "") +{ + if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) + && can_create_pseudo_p () && flag_finite_math_only + && !flag_trapping_math && flag_reciprocal_math) + { + rs6000_emit_swdiv (operands[0], operands[1], operands[2], true); + DONE; + } +}) (define_expand "neg<mode>2" [(set (match_operand:VEC_F 0 "vfloat_operand" "") |