diff options
author | H.J. Lu <hjl@gnu.org> | 1998-04-09 23:38:47 +0000 |
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committer | Jeff Law <law@gcc.gnu.org> | 1998-04-09 17:38:47 -0600 |
commit | b76c90cf74d37b7865a3df6cdc6026838e5934d2 (patch) | |
tree | 30bb1d309d23dd93dc1e5314176d504810c65b64 /gcc | |
parent | fcad5cf5e8bb2fc25e7971cf9f706581904f2a3e (diff) | |
download | gcc-b76c90cf74d37b7865a3df6cdc6026838e5934d2.zip gcc-b76c90cf74d37b7865a3df6cdc6026838e5934d2.tar.gz gcc-b76c90cf74d37b7865a3df6cdc6026838e5934d2.tar.bz2 |
i386.md (movqi+1): Handle invalid QI register.
* i386.md (movqi+1): Handle invalid QI register.
(movsf_push-1): Likewise.
From-SVN: r19073
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 143 |
2 files changed, 110 insertions, 38 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4cc32aa..5cfcaca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Fri Apr 10 00:36:31 1998 H.J. Lu (hjl@gnu.org) + + * i386.md (movqi+1): Handle invalid QI register. + (movsf_push-1): Likewise. + Thu Apr 9 16:53:59 1998 Nick Clifton <nickc@cygnus.com> * config/m32r/m32r.c: call_address_operand(): Only accept symbolic diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4426413..85a7ae0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1105,7 +1105,6 @@ return AS2 (xor%L0,%k0,%k0); if (operands[1] == const1_rtx - && !NON_QI_REG_P (operands[0]) && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) @@ -1114,8 +1113,14 @@ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) - /* Fastest way to change a 0 to a 1. */ - return AS1 (inc%B0,%0); + { + /* Fastest way to change a 0 to a 1. + If inc%B0 isn't allowed, use inc%L0. */ + if (NON_QI_REG_P (operands[0])) + return AS1 (inc%L0,%0); + else + return AS1 (inc%B0,%0); + } /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) @@ -1160,6 +1165,7 @@ return AS2 (xor%B0,%0,%0); if (operands[1] == const1_rtx + && ! NON_QI_REG_P (operands[0]) && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) @@ -7212,10 +7218,11 @@ byte_xor_operation: (define_expand "movsicc" [(match_dup 4) - (set (match_operand 0 "register_operand" "") + (parallel [(set (match_operand 0 "register_operand" "") (if_then_else:SI (match_operand 1 "comparison_operator" "") - (match_operand:SI 2 "nonimmediate_operand" "") - (match_operand:SI 3 "nonimmediate_operand" "")))] + (match_operand:SI 2 "general_operand" "") + (match_operand:SI 3 "general_operand" ""))) + (clobber (match_scratch:SI 4 "=&r"))])] "TARGET_CMOVE" " { @@ -7224,10 +7231,11 @@ byte_xor_operation: (define_expand "movhicc" [(match_dup 4) - (set (match_operand 0 "register_operand" "") + (parallel [(set (match_operand 0 "register_operand" "") (if_then_else:HI (match_operand 1 "comparison_operator" "") - (match_operand:HI 2 "nonimmediate_operand" "") - (match_operand:HI 3 "nonimmediate_operand" "")))] + (match_operand:HI 2 "general_operand" "") + (match_operand:HI 3 "general_operand" ""))) + (clobber (match_scratch:SI 4 "=&r"))])] "TARGET_CMOVE" " { @@ -7235,67 +7243,126 @@ byte_xor_operation: }") (define_insn "movsicc_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,&r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,&r,rm") (if_then_else:SI (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm") - (match_operand:SI 3 "nonimmediate_operand" "0,rm,rm")))] + [(cc0) (const_int 0)]) + (match_operand:SI 2 "general_operand" "rm,0,rm,g") + (match_operand:SI 3 "general_operand" "0,rm,rm,g"))) + (clobber (match_scratch:SI 4 "X,X,X,=&r"))] "TARGET_CMOVE" "* { - switch (which_alternative) + if (which_alternative == 0) { - case 0: /* r <- cond ? arg : r */ output_asm_insn (AS2 (cmov%C1,%2,%0), operands); - break; - - case 1: + } + else if (which_alternative == 1) + { /* r <- cond ? r : arg */ output_asm_insn (AS2 (cmov%c1,%3,%0), operands); - break; - - case 2: + } + else if (which_alternative == 2) + { /* r <- cond ? arg1 : arg2 */ output_asm_insn (AS2 (cmov%C1,%2,%0), operands); output_asm_insn (AS2 (cmov%c1,%3,%0), operands); - break; } - + else if (which_alternative == 3) + { + /* r <- cond ? arg1 : arg2 */ + rtx xops[3]; + + xops[0] = gen_label_rtx (); + xops[1] = gen_label_rtx (); + xops[2] = operands[1]; + + output_asm_insn (\"j%c2 %l0\", xops); + if (! rtx_equal_p (operands[0], operands[2])) + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[2]) == MEM) + { + output_asm_insn (AS2 (mov%z2,%2,%4), operands); + output_asm_insn (AS2 (mov%z2,%4,%0), operands); + } + else + output_asm_insn (AS2 (mov%z0,%2,%0), operands); + output_asm_insn (\"jmp %l1\", xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (xops[0])); + if (! rtx_equal_p (operands[0], operands[3])) + { + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[3]) == MEM) + { + output_asm_insn (AS2 (mov%z3,%3,%4), operands); + output_asm_insn (AS2 (mov%z3,%4,%0), operands); + } + else + output_asm_insn (AS2 (mov%z0,%3,%0), operands); + } + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (xops[1])); + } RET; }") (define_insn "movhicc_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,&r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,&r,rm") (if_then_else:HI (match_operator 1 "comparison_operator" - [(cc0) (const_int 0)]) - (match_operand:HI 2 "nonimmediate_operand" "rm,0,rm") - (match_operand:HI 3 "nonimmediate_operand" "0,rm,rm")))] + [(cc0) (const_int 0)]) + (match_operand:HI 2 "general_operand" "rm,0,rm,g") + (match_operand:HI 3 "general_operand" "0,rm,rm,g"))) + (clobber (match_scratch:SI 4 "X,X,X,=&r"))] "TARGET_CMOVE" "* { - switch (which_alternative) + if (which_alternative == 0) { - case 0: /* r <- cond ? arg : r */ output_asm_insn (AS2 (cmov%C1,%2,%0), operands); - break; - - case 1: + } + else if (which_alternative == 1) + { /* r <- cond ? r : arg */ output_asm_insn (AS2 (cmov%c1,%3,%0), operands); - break; - - case 2: + } + else if (which_alternative == 2) + { /* r <- cond ? arg1 : arg2 */ output_asm_insn (AS2 (cmov%C1,%2,%0), operands); output_asm_insn (AS2 (cmov%c1,%3,%0), operands); - break; } - + else if (which_alternative == 3) + { + /* r <- cond ? arg1 : arg2 */ + rtx xops[3]; + + xops[0] = gen_label_rtx (); + xops[1] = gen_label_rtx (); + xops[2] = operands[1]; + + output_asm_insn (\"j%c2 %l0\", xops); + if (! rtx_equal_p (operands[0], operands[2])) + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[2]) == MEM) + { + output_asm_insn (AS2 (mov%z2,%2,%4), operands); + output_asm_insn (AS2 (mov%z2,%4,%0), operands); + } + else + output_asm_insn (AS2 (mov%z0,%2,%0), operands); + output_asm_insn (\"jmp %l1\", xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (xops[0])); + if (! rtx_equal_p (operands[0], operands[3])) + { + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[3]) == MEM) + { + output_asm_insn (AS2 (mov%z3,%3,%4), operands); + output_asm_insn (AS2 (mov%z3,%4,%0), operands); + } + else + output_asm_insn (AS2 (mov%z0,%3,%0), operands); + } + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (xops[1])); + } RET; }") - ;; We need to disable the FP forms of these since they do not support ;; memory as written, but no input reloads are permitted for insns ;; that use cc0. Also, movxfcc is not present. |