(attribute "type"): Add new type, "branch".

(attribute "length"): New attribute; put on all insns that don't have default
length.
(branch patterns): If conditional branch won't reach, take conditional branch
around an unconditional branch.

(plus): Split (plus (COMPARISON FOO ...) ...) at FOO.

From-SVN: r5148

1 files changed, 278 insertions, 117 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d04b249..5de6f20 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -22,9 +22,20 @@
 
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations.
-(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
+(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr,branch"
   (const_string "integer"))
 
+;; Length (in bytes).
+(define_attr "length" ""
+  (if_then_else (eq_attr "type" "branch")
+		(if_then_else (and (ge (minus (pc) (match_dup 0))
+				       (const_int -32768))
+				   (lt (minus (pc) (match_dup 0))
+				       (const_int 32767)))
+			      (const_int 8)
+			      (const_int 12))
+		(const_int 4)))
+
 ;; Memory delivers its result in two cycles.
 (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
 
@@ -433,7 +444,8 @@
   [(set (match_operand:SI 0 "register_operand" "=&r")
 	(ffs:SI (match_operand:SI 1 "register_operand" "r")))]
   ""
-  "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
+  "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32"
+  [(set_attr "length" "16")])
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -521,7 +533,8 @@
 	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "const_int_operand" "N")))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
-  "srai %0,%1,%p2\;aze %0,%0")
+  "srai %0,%1,%p2\;aze %0,%0"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -530,7 +543,8 @@
    (clobber (match_scratch:SI 3 "=r"))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
   "srai %3,%1,%p2\;aze. %3,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -540,7 +554,8 @@
 	(div:SI (match_dup 1) (match_dup 2)))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
   "srai %0,%1,%p2\;aze. %0,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -667,7 +682,7 @@
    andil. %0,%1,%b2
    andiu. %0,%1,%u2
    rlinm. %0,%1,0,%m2,%M2"
-  [(set_attr "type" "compare,compare,compare,delayed_compare")]) 
+  [(set_attr "type" "compare,compare,compare,delayed_compare")])
 
 ;; Take a AND with a constant that cannot be done in a single insn and try to
 ;; split it into two insns.  This does not verify that the insns are valid
@@ -1287,7 +1302,8 @@
   ""
   "@
    sle %0,%1,%2
-   sli %0,%1,%h2")
+   sli %0,%1,%h2"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -1984,7 +2000,8 @@
   ""
   "@
    a %L0,%L1,%L2\;ae %0,%1,%2
-   ai %L0,%L1,%2\;a%G2e %0,%1")
+   ai %L0,%L1,%2\;a%G2e %0,%1"
+  [(set_attr "length" "8")])
 
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -1993,13 +2010,15 @@
   ""
   "@
    sf %L0,%L2,%L1\;sfe %0,%2,%1
-   sfi %L0,%L2,%1\;sf%G1e %0,%2")
+   sfi %L0,%L2,%1\;sf%G1e %0,%2"
+  [(set_attr "length" "8")])
 
 (define_insn "negdi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
   ""
-  "sfi %L0,%L1,0\;sfze %0,%1")
+  "sfi %L0,%L1,0\;sfze %0,%1"
+  [(set_attr "length" "8")])
 
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -2007,7 +2026,8 @@
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
    (clobber (match_scratch:SI 3 "=q"))]
   ""
-  "mul %0,%1,%2\;mfmq %L0")
+  "mul %0,%1,%2\;mfmq %L0"
+  [(set_attr "length" "8")])
 
 ;; If operands 0 and 2 are in the same register, we have a problem.  But
 ;; operands 0 and 1 (the usual case) can be in the same register.  That's
@@ -2022,7 +2042,8 @@
    sli %0,%L1,%h2\;cal %L0,0(0)
    sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
    sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
+   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
+  [(set_attr "length" "8")])
 
 (define_insn "lshrdi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
@@ -2034,7 +2055,8 @@
    cal %0,0(0)\;s%A2i %L0,%1,%h2
    sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
    sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2")
+   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
+  [(set_attr "length" "8")])
 
 ;; Shift by a variable amount is too complex to be worth open-coding.  We
 ;; just handle shifts by constants.
@@ -2058,7 +2080,8 @@
   ""
   "@
    srai %0,%1,31\;srai %L0,%1,%h2
-   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2")
+   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
+  [(set_attr "length" "8")])
 
 ;; Now define ways of moving data around.
 ;;
@@ -2235,7 +2258,8 @@
    ai %0,%1,0
    l%U1%X1 %0,%1
    st%U0%U1 %1,%0"
-  [(set_attr "type" "*,*,*,compare,*,*,load,*")])
+  [(set_attr "type" "*,*,*,compare,*,*,load,*")
+   (set_attr "length" "*,*,12,*,8,*,*,*")])
 
 ;; For floating-point, we normally deal with the floating-point registers.
 ;; The sole exception is that parameter passing can produce floating-point
@@ -2351,7 +2375,8 @@
    fmr %0,%1
    lfs%U1%X1 %0,%1
    frsp %1,%1\;stfs%U0%X0 %1,%0"
-  [(set_attr "type" "fp,load,*")])
+  [(set_attr "type" "fp,load,*")
+   (set_attr "length" "*,*,8")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -2457,7 +2482,8 @@
   "@
    #
    l %0,%1\;l %L0,%L1"
-  [(set_attr "type" "*,load")])
+  [(set_attr "type" "*,load")
+   (set_attr "length" "*,8")])
 
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -2535,7 +2561,8 @@
       return \"st%U0 %1,%0\;st %L1,%L0\";
     }
 }"
-  [(set_attr "type" "*,load,*")])
+  [(set_attr "type" "*,load,*")
+   (set_attr "length" "8")])
 
 ;; TImode is similar, except that we usually want to compute the address into
 ;; a register and use lsi/stsi (the exception is during reload).  MQ is also
@@ -2616,7 +2643,8 @@
 	return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
     }
 }"
-  [(set_attr "type" "*,load,load,*,*")])
+  [(set_attr "type" "*,load,load,*,*")
+   (set_attr "length" "*,16,16,*,16")])
 
 (define_expand "load_multiple"
   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
@@ -2663,7 +2691,8 @@
   /* We have to handle the case where the pseudo used to contain the address
      is assigned to one of the output registers.  In that case, do the
      lsi, but then load the correct value.  This is a bit of a mess, but is
-     the best we can do.  */
+     the best we can do.
+     We set the length attribute to the maximum possible size (8 bytes).  */
   static char result[100];
   char newload[40];
   int i;
@@ -2681,8 +2710,10 @@
 
   return result;
 }"
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
+
 (define_expand "store_multiple"
   [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
 			  (match_operand:SI 1 "" ""))
@@ -3059,7 +3090,8 @@
   ""
   "@
    brl\;l 2,20(1)
-   bl %z0\;cror %.,%.,%.")
+   bl %z0\;cror %.,%.,%."
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand 0 "" "=fg")
@@ -3077,7 +3109,8 @@
   ""
   "@
    brl\;l 2,20(1)
-   bl %z1\;cror %.,%.,%.")
+   bl %z1\;cror %.,%.,%."
+  [(set_attr "length" "8")])
 
 ;; Call subroutine returning any type.
 
@@ -3566,7 +3599,8 @@
 			   [(match_operand 2 "cc_reg_operand" "y")
 			    (const_int 0)]))]
   ""
-  "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
+  "%D1mfcr %0\;rlinm %0,%0,%J1,31,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -3578,7 +3612,8 @@
 	(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
   ""
   "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
-  [(set_attr "type" "delayed_compare")])
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -3602,7 +3637,8 @@
   operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
 
   return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
-}")
+}"
+ [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -3632,7 +3668,8 @@
 
   return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
 }"
-  [(set_attr "type" "delayed_compare")])
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
 
 ;; If we are comparing the result of two comparisons, this can be done
 ;; using creqv or crxor.
@@ -3663,7 +3700,8 @@
     return \"%C1%C3crxor %E0,%j1,%j3\";
   else
     return \"%C1%C3creqv %E0,%j1,%j3\";
-}")
+}"
+  [(set_attr "length" "12")])
 
 ;; There is a 3 cycle delay between consecutive mfcr instructions
 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
@@ -3678,7 +3716,8 @@
 			   [(match_operand 5 "cc_reg_operand" "y")
 			    (const_int 0)]))]
    "REGNO (operands[2]) != REGNO (operands[5])"
-   "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
+   "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31"
+   [(set_attr "length" "20")])
 
 ;; There are some scc insns that can be done directly, without a compare.
 ;; These are faster because they don't involve the communications between
@@ -3705,7 +3744,8 @@
    sfi %3,%1,0\;ae %0,%3,%1
    xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
    xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
-   sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
+   sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0"
+  [(set_attr "length" "12,8,12,12,12")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
@@ -3723,7 +3763,23 @@
    xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
    xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
    sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12,8,12,12,12")])
+
+;; We have insns of the form shown by the first define_insn below.  If
+;; there is something inside the comparison operation, we must split it.
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(plus:SI (match_operator 1 "comparison_operator"
+				 [(match_operand:SI 2 "" "")
+				  (match_operand:SI 3
+						    "reg_or_cint_operand" "")])
+		 (match_operand:SI 4 "gpc_reg_operand" "")))
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "! gpc_reg_operand (operands[2], SImode)"
+  [(set (match_dup 5) (match_dup 2))
+   (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
+			       (match_dup 4)))])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
@@ -3737,7 +3793,8 @@
    sfi %4,%1,0\;aze %0,%3
    xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
    xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
-   sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
+   sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3"
+  [(set_attr "length" "12,8,12,12,12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
@@ -3755,7 +3812,8 @@
    xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
    xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
    sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12,8,12,12,12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
@@ -3775,7 +3833,8 @@
    xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
    xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
    sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12,8,12,12,12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
@@ -3787,7 +3846,8 @@
    ai %0,%1,-1\;sfe %0,%0,%0
    xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
    xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
-   sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
+   sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0"
+   [(set_attr "length" "12,8,12,12,12")])
 
 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
 (define_insn ""
@@ -3798,7 +3858,8 @@
 		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
-  "ai %3,%1,-1\;aze %0,%2")
+  "ai %3,%1,-1\;aze %0,%2"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -3811,7 +3872,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "ai %3,%1,-1\;aze. %3,%2"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
@@ -3827,7 +3889,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "ai %3,%1,-1\;aze. %0,%2"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -3837,7 +3900,8 @@
   ""
   "@
    doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
-   ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
+   ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
@@ -3852,7 +3916,8 @@
   "@
    doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
    ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
-  [(set_attr "type" "delayed_compare,compare")])
+  [(set_attr "type" "delayed_compare,compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -3863,7 +3928,8 @@
   ""
   "@
    doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
-   srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
+   srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -3877,7 +3943,8 @@
   "@
    doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
    srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
@@ -3893,7 +3960,8 @@
   "@
    doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
    srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -3902,14 +3970,16 @@
   ""
   "@
    doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
-   ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
+   ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
-  "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
+  "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -3921,7 +3991,8 @@
 	(leu:SI (match_dup 1) (match_dup 2)))]
    ""
   "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -3930,7 +4001,8 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
-  "sf%I2 %4,%1,%2\;aze %0,%3")
+  "sf%I2 %4,%1,%2\;aze %0,%3"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -3942,7 +4014,8 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
@@ -3956,14 +4029,16 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
-  "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
+  "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0"
+   [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -3973,7 +4048,8 @@
 		(match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
-  "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
+  "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -3986,7 +4062,8 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
@@ -4001,14 +4078,16 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
+  "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31"
+   [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 3 "cc_reg_operand" "=x")
@@ -4020,7 +4099,8 @@
 	(lt:SI (match_dup 1) (match_dup 2)))]
   ""
   "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
-  [(set_attr "type" "delayed_compare")])
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4029,7 +4109,8 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
-  "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
+  "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "cc_reg_operand" "=x")
@@ -4041,7 +4122,8 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 5 "cc_reg_operand" "=x")
@@ -4055,14 +4137,16 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
+  "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4071,7 +4155,8 @@
   ""
   "@
    sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
-   ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
+   ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
@@ -4085,7 +4170,8 @@
   "@
    sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
    ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
@@ -4098,7 +4184,8 @@
   sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
   sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
   ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
-  ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
+  ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3"
+ [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
@@ -4114,7 +4201,8 @@
    sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
    ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
    ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
@@ -4132,7 +4220,8 @@
    sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
    ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
    ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4141,7 +4230,8 @@
   ""
   "@
    sf %0,%2,%1\;sfe %0,%0,%0
-   ai %0,%1,%n2\;sfe %0,%0,%0")
+   ai %0,%1,%n2\;sfe %0,%0,%0"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4149,7 +4239,8 @@
 	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
-  "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
+  "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3"
+   [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
@@ -4162,7 +4253,8 @@
    (clobber (match_scratch:SI 3 "=r"))]
   ""
   "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4171,7 +4263,8 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
-  "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
+  "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -4183,7 +4276,8 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
@@ -4197,14 +4291,16 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
-  "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
+  "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0"
+  [(set_attr "length" "12")])
 
 ;; This is (and (neg (ge X (const_int 0))) Y).
 (define_insn ""
@@ -4216,7 +4312,8 @@
 		(match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
-  "srai %3,%1,31\;andc %0,%2,%3")
+  "srai %3,%1,31\;andc %0,%2,%3"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -4230,7 +4327,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "srai %3,%1,31\;andc. %3,%2,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
@@ -4248,7 +4346,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "srai %3,%1,31\;andc. %0,%2,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4257,7 +4356,8 @@
   ""
   "@
    sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
-   ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
+   ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
@@ -4271,7 +4371,8 @@
   "@
    sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
    ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4282,7 +4383,8 @@
   ""
   "@
    sf %4,%2,%1\;aze %0,%3
-   ai %4,%1,%n2\;aze %0,%3")
+   ai %4,%1,%n2\;aze %0,%3"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -4296,7 +4398,8 @@
   "@
    sf %4,%2,%1\;aze. %4,%3
    ai %4,%1,%n2\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
@@ -4312,7 +4415,8 @@
   "@
    sf %4,%2,%1\;aze. %0,%3
    ai %4,%1,%n2\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4321,7 +4425,8 @@
   ""
   "@
    sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
-   sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
+   sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4333,7 +4438,8 @@
   ""
   "@
    sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
-   ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
+   ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -4348,7 +4454,8 @@
   "@
    sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
    ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
@@ -4365,14 +4472,16 @@
   "@
    sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
    ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (const_int 0)))]
   ""
-  "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
+  "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
@@ -4384,14 +4493,16 @@
 	(gt:SI (match_dup 1) (const_int 0)))]
   ""
   "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
-  [(set_attr "type" "delayed_compare")])
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
   ""
-  "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
+  "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -4403,7 +4514,8 @@
 	(gt:SI (match_dup 1) (match_dup 2)))]
   ""
   "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
-  [(set_attr "type" "delayed_compare")])
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4412,7 +4524,8 @@
 		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
-  "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
+  "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -4424,7 +4537,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
@@ -4438,7 +4552,8 @@
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4447,7 +4562,8 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
-  "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
+  "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -4459,7 +4575,8 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
@@ -4473,28 +4590,32 @@
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (const_int 0))))]
   ""
-  "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
+  "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
   ""
-  "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
+  "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
-  "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
+  "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0"
+  [(set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -4506,7 +4627,8 @@
 	(gtu:SI (match_dup 1) (match_dup 2)))]
   ""
   "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
@@ -4518,7 +4640,8 @@
   "@
    ai %4,%1,%k2\;aze %0,%3
    sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
-   sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
+   sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3"
+  [(set_attr "length" "8,12,12")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
@@ -4533,7 +4656,8 @@
    ai %4,%1,%k2\;aze. %0,%3
    sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
    sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8,12,12")])
 
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x")
@@ -4550,14 +4674,16 @@
    ai %4,%1,%k2\;aze. %0,%3
    sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
    sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
-  [(set_attr "type" "compare")])
+  [(set_attr "type" "compare")
+   (set_attr "length" "8,12,12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
-  "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
+  "sf%I2 %0,%1,%2\;sfe %0,%0,%0"
+  [(set_attr "length" "8")])
 
 ;; Define both directions of branch and return.  If we need a reload
 ;; register, we'd rather use CR0 since it is much easier to copy a
@@ -4572,7 +4698,15 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "%C1bc %t1,%j1,%0")
+  "*
+{
+  if (get_attr_length (insn) == 8)
+    return \"%C1bc %t1,%j1,%l0\";
+  else
+    return \"%C1bc %T1,%j1,$+8\;b %l0\";
+}"
+  [(set_attr "type" "branch")])
+
 
 (define_insn ""
   [(set (pc)
@@ -4583,7 +4717,8 @@
 		      (return)
 		      (pc)))]
   "direct_return ()"
-  "%C0bcr %t0,%j0")
+  "%C0bcr %t0,%j0"
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (pc)
@@ -4594,7 +4729,14 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "%C1bc %T1,%j1,%0")
+  "*
+{
+  if (get_attr_length (insn) == 8)
+    return \"%C1bc %T1,%j1,%l0\";
+  else
+    return \"%C1bc %t1,%j1,$+8\;b %l0\";
+}"
+  [(set_attr "type" "branch")])
 
 (define_insn ""
   [(set (pc)
@@ -4605,7 +4747,8 @@
 		      (pc)
 		      (return)))]
   "direct_return ()"
-  "%C0bcr %T0,%j0")
+  "%C0bcr %T0,%j0"
+  [(set_attr "length" "8")])
 
 ;; Unconditional branch and return.
 
@@ -4681,10 +4824,16 @@
    (clobber (match_scratch:CC 3 "=X,&x,&x"))
    (clobber (match_scratch:SI 4 "=X,X,r"))]
   ""
-  "@
-   bdn %l2
-   #
-   #")
+  "*
+{
+  if (which_alternative == 1)
+    return \"#\";
+  else if (get_attr_length (insn) == 8)
+    return \"bdn %l2\";
+  else
+    return \"bdz $+8\;b %l2\";
+}"
+  [(set_attr "type" "branch")])
 			       
 ;; Similar, but we can use GE since we have a REG_NONNEG.
 (define_insn ""
@@ -4698,10 +4847,16 @@
    (clobber (match_scratch:CC 3 "=X,&x,&X"))
    (clobber (match_scratch:SI 4 "=X,X,r"))]
   "find_reg_note (insn, REG_NONNEG, 0)"
-  "@
-   bdn %l2
-   #
-   #")
+  "*
+{
+  if (which_alternative == 1)
+    return \"#\";
+  else if (get_attr_length (insn) == 8)
+    return \"bdn %l2\";
+  else
+    return \"bdz $+8\;b %l2\";
+}"
+  [(set_attr "type" "branch")])
 			       
 (define_insn ""
   [(set (pc)
@@ -4714,10 +4869,16 @@
    (clobber (match_scratch:CC 3 "=X,&x,&x"))
    (clobber (match_scratch:SI 4 "=X,X,r"))]
   ""
-  "@
-   bdz %l2
-   #
-   #")
+  "*
+{
+  if (which_alternative == 1)
+    return \"#\";
+  else if (get_attr_length (insn) == 8)
+    return \"bdz %l2\";
+  else
+    return \"bdn $+8\;b %l2\";
+}"
+  [(set_attr "type" "branch")])
 
 (define_split
   [(set (pc)