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| author | Doug Evans <dje@gnu.org> | 1995-05-15 01:32:32 +0000 |
|---|---|---|
| committer | Doug Evans <dje@gnu.org> | 1995-05-15 01:32:32 +0000 |
| commit | b10ed55576e7a0e0f861eb5e8b8e34e1d194cb13 (patch) | |
| tree | 3efda1e24ecd618e068a96a545915aa30df8d499 /gcc | |
| parent | ba68fc32bc83b21b54c7d9106bc7f0e81f07f1b1 (diff) | |
| download | gcc-b10ed55576e7a0e0f861eb5e8b8e34e1d194cb13.zip gcc-b10ed55576e7a0e0f861eb5e8b8e34e1d194cb13.tar.gz gcc-b10ed55576e7a0e0f861eb5e8b8e34e1d194cb13.tar.bz2 | |
(movsicc, case NE): Don't generate unrecognizable insn.
(movdicc, case NE): Likewise.
From-SVN: r9685
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/alpha/alpha.md | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 4f46a13..aa745ab 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -2234,13 +2234,18 @@ " { rtx op0,op1; - enum rtx_code code = GET_CODE (operands[1]); + enum rtx_code code = GET_CODE (operands[1]), code2 = NE; if (alpha_compare_fp_p) FAIL; switch (code) { - case EQ: case NE: case LE: case LT: + case EQ: case LE: case LT: + op0 = alpha_compare_op0; + op1 = alpha_compare_op1; + break; + case NE: + code = code2 = EQ; op0 = alpha_compare_op0; op1 = alpha_compare_op1; break; @@ -2259,7 +2264,7 @@ } operands[1] = gen_rtx (code, DImode, op0, op1); operands[4] = gen_reg_rtx (DImode); - operands[5] = gen_rtx (NE, VOIDmode, operands[4], CONST0_RTX (DImode)); + operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode)); }") (define_expand "movdicc" @@ -2272,13 +2277,18 @@ " { rtx op0,op1; - enum rtx_code code = GET_CODE (operands[1]); + enum rtx_code code = GET_CODE (operands[1]), code2 = NE; if (alpha_compare_fp_p) FAIL; switch (code) { - case EQ: case NE: case LE: case LT: + case EQ: case LE: case LT: + op0 = alpha_compare_op0; + op1 = alpha_compare_op1; + break; + case NE: + code = code2 = EQ; op0 = alpha_compare_op0; op1 = alpha_compare_op1; break; @@ -2297,7 +2307,7 @@ } operands[1] = gen_rtx (code, DImode, op0, op1); operands[4] = gen_reg_rtx (DImode); - operands[5] = gen_rtx (NE, VOIDmode, operands[4], CONST0_RTX (DImode)); + operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode)); }") (define_expand "movsfcc" |