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| author | Catherine Moore <clm@codesourcery.com> | 2012-08-04 18:16:57 -0400 |
|---|---|---|
| committer | Sandra Loosemore <sandra@gcc.gnu.org> | 2012-08-04 18:16:57 -0400 |
| commit | b0e7f54dc77a943e2bd28d4f61c5d8e2afdb8f7a (patch) | |
| tree | da47f76914b6c01896328ee7efd5b97c6d9400d7 /gcc | |
| parent | b6f1f6eaed3683e873c1b15f645e5295dcddcdaf (diff) | |
| download | gcc-b0e7f54dc77a943e2bd28d4f61c5d8e2afdb8f7a.zip gcc-b0e7f54dc77a943e2bd28d4f61c5d8e2afdb8f7a.tar.gz gcc-b0e7f54dc77a943e2bd28d4f61c5d8e2afdb8f7a.tar.bz2 | |
xlr.md (ir_xlr_alu_clz): New insn_reservation.
2012-08-04 Catherine Moore <clm@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
gcc/
* config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation.
(ir_xlr_alu): Remove clz.
* config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY.
Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>
From-SVN: r190146
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips-cpus.def | 2 | ||||
| -rw-r--r-- | gcc/config/mips/xlr.md | 7 |
3 files changed, 14 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c849368..b8f0a86 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2012-08-04 Catherine Moore <clm@codesourcery.com> + Sandra Loosemore <sandra@codesourcery.com> + + * config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation. + (ir_xlr_alu): Remove clz. + * config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY. + 2012-08-04 Richard Earnshaw <rearnsha@arm.com> * arm.c (arm_gen_constant): Use SImode when preparing operands for diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 62b1a19..e8dc5a7 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -142,7 +142,7 @@ MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0) +MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY) /* MIPS64 Release 2 processors. */ diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md index 1420469..59f8633 100644 --- a/gcc/config/mips/xlr.md +++ b/gcc/config/mips/xlr.md @@ -28,10 +28,15 @@ (eq_attr "type" "slt")) "xlr_main_pipe") +(define_insn_reservation "ir_xlr_alu_clz" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "clz")) + "xlr_main_pipe") + ;; Integer arithmetic instructions. (define_insn_reservation "ir_xlr_alu" 1 (and (eq_attr "cpu" "xlr") - (eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) + (eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) "xlr_main_pipe") ;; Integer arithmetic instructions. |