diff options
| author | Richard Henderson <rth@cygnus.com> | 1998-08-09 18:23:59 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1998-08-09 18:23:59 -0700 |
| commit | b08b85c4a0b590394116fdb5acc8d4e2068544b1 (patch) | |
| tree | c72d7c4cdc65b24f406bd40c1239a41a590e3bba /gcc | |
| parent | 4ef30178c058bfc6e32f59ce1f0dde110bf6e9c1 (diff) | |
| download | gcc-b08b85c4a0b590394116fdb5acc8d4e2068544b1.zip gcc-b08b85c4a0b590394116fdb5acc8d4e2068544b1.tar.gz gcc-b08b85c4a0b590394116fdb5acc8d4e2068544b1.tar.bz2 | |
alpha.md (extxl+1,+2): New patterns to work around combine lossage.
* alpha.md (extxl+1,+2): New patterns to work around
combine lossage.
From-SVN: r21651
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 23 |
2 files changed, 28 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 716b79d..e1a6e38 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Mon Aug 10 01:21:01 1998 Richard Henderson <rth@cygnus.com> + + * alpha.md (extxl+1,+2): New patterns to work around + combine lossage. + Sat Aug 8 19:20:22 1998 Gary Thomas (gdt@linuxppc.org) * rs6000.c (rs6000_allocate_stack_space) Fix typo which diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index a92a847..c2eeaee 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -1495,6 +1495,29 @@ "ext%M2l %r1,%3,%0" [(set_attr "type" "shift")]) +;; Combine has some strange notion of preserving existing undefined behaviour +;; in shifts larger than a word size. So capture these patterns that it +;; should have turned into zero_extracts. + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") + (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") + (const_int 3))) + (match_operand:DI 3 "mode_mask_operand" "n")))] + "" + "ext%U3l %1,%2,%0" + [(set_attr "type" "shift")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") + (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") + (const_int 3))))] + "" + "extql %1,%2,%0" + [(set_attr "type" "shift")]) + (define_insn "extqh" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI |