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| author | H.J. Lu <hongjiu.lu@intel.com> | 2012-10-02 19:49:01 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2012-10-02 12:49:01 -0700 |
| commit | a91529c4eb62ef76365f45cd08287f6a91c76512 (patch) | |
| tree | f65bd0479959b16e5a2019d572b0213f02dff6b0 /gcc | |
| parent | dccb154f149a2d99eb06fed4e2a32479f2d5174c (diff) | |
| download | gcc-a91529c4eb62ef76365f45cd08287f6a91c76512.zip gcc-a91529c4eb62ef76365f45cd08287f6a91c76512.tar.gz gcc-a91529c4eb62ef76365f45cd08287f6a91c76512.tar.bz2 | |
Check SSE and YMM state support for -march=native
2012-10-02 H.J. Lu <hongjiu.lu@intel.com>
PR target/54741
* config/i386/driver-i386.c (XCR_XFEATURE_ENABLED_MASK): New.
(XSTATE_FP): Likewise.
(XSTATE_SSE): Likewise.
(XSTATE_YMM): Likewise.
(host_detect_local_cpu): Disable AVX, AVX2, FMA, FMA4 and XOP if
SSE and YMM states aren't supported.
From-SVN: r191998
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/i386/driver-i386.c | 22 |
2 files changed, 32 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 46cdf7d..4612f03 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2012-10-02 H.J. Lu <hongjiu.lu@intel.com> + + PR target/54741 + * config/i386/driver-i386.c (XCR_XFEATURE_ENABLED_MASK): New. + (XSTATE_FP): Likewise. + (XSTATE_SSE): Likewise. + (XSTATE_YMM): Likewise. + (host_detect_local_cpu): Disable AVX, AVX2, FMA, FMA4 and XOP if + SSE and YMM states aren't supported. + 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index bda4e02..4dffc51 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -390,6 +390,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_hle = 0, has_rtm = 0; unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; + unsigned int has_osxsave = 0; bool arch; @@ -431,6 +432,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_sse4_1 = ecx & bit_SSE4_1; has_sse4_2 = ecx & bit_SSE4_2; has_avx = ecx & bit_AVX; + has_osxsave = ecx & bit_OSXSAVE; has_cmpxchg16b = ecx & bit_CMPXCHG16B; has_movbe = ecx & bit_MOVBE; has_popcnt = ecx & bit_POPCNT; @@ -460,6 +462,26 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_adx = ebx & bit_ADX; } + /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ +#define XCR_XFEATURE_ENABLED_MASK 0x0 +#define XSTATE_FP 0x1 +#define XSTATE_SSE 0x2 +#define XSTATE_YMM 0x4 + if (has_osxsave) + asm (".byte 0x0f; .byte 0x01; .byte 0xd0" + : "=a" (eax), "=d" (edx) + : "c" (XCR_XFEATURE_ENABLED_MASK)); + + /* Check if SSE and YMM states are supported. */ + if ((eax & (XSTATE_SSE | XSTATE_YMM)) == (XSTATE_SSE | XSTATE_YMM)) + { + has_avx = 0; + has_avx2 = 0; + has_fma = 0; + has_fma4 = 0; + has_xop = 0; + } + /* Check cpuid level of extended features. */ __cpuid (0x80000000, ext_level, ebx, ecx, edx); |