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| author | Jim Wilson <jimw@sifive.com> | 2019-11-05 22:34:40 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-11-05 14:34:40 -0800 |
| commit | a81ffd93b83c4be250514ff385b5b88fa5c3835b (patch) | |
| tree | 9106ef9f8689bb7b61d0d78c63a1ad65f8dffe08 /gcc | |
| parent | 8aa76bb74696d0987e04a82ebcbc44f745ce788d (diff) | |
| download | gcc-a81ffd93b83c4be250514ff385b5b88fa5c3835b.zip gcc-a81ffd93b83c4be250514ff385b5b88fa5c3835b.tar.gz gcc-a81ffd93b83c4be250514ff385b5b88fa5c3835b.tar.bz2 | |
Allow libcalls for complex memcpy when optimizing for size.
The RISC-V backend wants to use a libcall when optimizing for size if
more than 6 instructions are needed. Emit_move_complex asks for no
libcalls. This case requires 8 insns for rv64 and 16 insns for rv32,
so we get fallback code that emits a loop. Commit_one_edge_insertion
doesn't allow code inserted for a phi node on an edge to end with a
branch, and so this triggers an assertion. This problem goes away if
we allow libcalls when optimizing for size, which gives the code the
RISC-V backend wants, and avoids triggering the assert.
gcc/
PR middle-end/92263
* expr.c (emit_move_complex): Only use BLOCK_OP_NO_LIBCALL when
optimize_insn_for_speed_p is true.
gcc/testsuite/
PR middle-end/92263
* gcc.dg/pr92263.c: New.
From-SVN: r277861
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/expr.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr92263.c | 28 |
4 files changed, 43 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f3deffc..4312d12 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-11-05 Jim Wilson <jimw@sifive.com> + + PR middle-end/92263 + * expr.c (emit_move_complex): Only use BLOCK_OP_NO_LIBCALL when + optimize_insn_for_speed_p is true. + 2019-11-05 Martin Sebor <msebor@redhat.com> PR middle-end/92333 @@ -3571,11 +3571,13 @@ emit_move_complex (machine_mode mode, rtx x, rtx y) rtx_insn *ret; /* For memory to memory moves, optimal behavior can be had with the - existing block move logic. */ + existing block move logic. But use normal expansion if optimizing + for size. */ if (MEM_P (x) && MEM_P (y)) { emit_block_move (x, y, gen_int_mode (GET_MODE_SIZE (mode), Pmode), - BLOCK_OP_NO_LIBCALL); + (optimize_insn_for_speed_p() + ? BLOCK_OP_NO_LIBCALL : BLOCK_OP_NORMAL)); return get_last_insn (); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4932615..f34ed08 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-11-05 Jim Wilson <jimw@sifive.com> + + PR middle-end/92263 + * gcc.dg/pr92263.c: New. + 2019-11-05 Martin Sebor <msebor@redhat.com> PR middle-end/92333 diff --git a/gcc/testsuite/gcc.dg/pr92263.c b/gcc/testsuite/gcc.dg/pr92263.c new file mode 100644 index 0000000..a79dfd1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr92263.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-fno-tree-dce -fno-tree-forwprop -Os -ffloat-store" } */ + +extern long double cabsl (_Complex long double); + +typedef struct { + int nsant, nvqd; + _Complex long double *vqd; +} vsorc_t; +vsorc_t vsorc; + +void foo(int next_job, int ain_num, int iped, long t) { + long double zpnorm; + + while (!next_job) + if (ain_num) + { + if (iped == 1) + zpnorm = 0.0; + int indx = vsorc.nvqd-1; + vsorc.vqd[indx] = t*1.0fj; + if (cabsl(vsorc.vqd[indx]) < 1.e-20) + vsorc.vqd[indx] = 0.0fj; + zpnorm = t; + if (zpnorm > 0.0) + iped = vsorc.nsant; + } +} |