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| author | Andrew Cagney <cagney@b1.cygnus.com> | 1998-11-09 16:50:18 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1998-11-09 08:50:18 -0800 |
| commit | a3bc83cc3028fb98df61d1fde7e62f05295cf894 (patch) | |
| tree | eeffac9b9ca0e06059c2bf394c0927aeb11a9049 /gcc | |
| parent | b8b2d50de916d20189497865c6d4c0d3143d1ff0 (diff) | |
| download | gcc-a3bc83cc3028fb98df61d1fde7e62f05295cf894.zip gcc-a3bc83cc3028fb98df61d1fde7e62f05295cf894.tar.gz gcc-a3bc83cc3028fb98df61d1fde7e62f05295cf894.tar.bz2 | |
Misc mips16 bug fixes found by gcc/gdb testsuites.
* mips.c (function_prologue): When TARGET_MIPS16, adjust the register
offset in the .mask pseudo to compensate for frame pointer adjustments.
(mips16_fp_args, build_mips16_call_stub): For little endian, do not
word swap arguments moved to/from FP registers.
* mips16.S (DFREVCMP): Reverse arguments to OPCODE.
From-SVN: r23586
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 40 | ||||
| -rw-r--r-- | gcc/config/mips/mips16.S | 2 |
3 files changed, 39 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9d15a58..b3072f5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +Mon Nov 9 16:37:52 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * mips.c (function_prologue): When TARGET_MIPS16, adjust the register + offset in the .mask pseudo to compensate for frame pointer adjustments. + (mips16_fp_args, build_mips16_call_stub): For little endian, do not + word swap arguments moved to/from FP registers. + * mips16.S (DFREVCMP): Reverse arguments to OPCODE. + Mon Nov 9 09:47:06 PST 1998 Jeff Law (law@cygnus.com) * version.c: Bump for snapshot. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 5eb1bc4..93dd1fb 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -6085,7 +6085,10 @@ function_prologue (file, size) fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n", current_frame_info.mask, - current_frame_info.gp_save_offset, + ((frame_pointer_needed && TARGET_MIPS16) + ? (current_frame_info.gp_save_offset + - current_function_outgoing_args_size) + : current_frame_info.gp_save_offset), current_frame_info.fmask, current_frame_info.fp_save_offset); } @@ -7434,9 +7437,14 @@ mips16_fp_args (file, fp_code, from_fp_p) { if ((fparg & 1) != 0) ++fparg; - fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, - reg_names[gparg], reg_names[fparg + 1], s, - reg_names[gparg + 1], reg_names[fparg]); + if (TARGET_BIG_ENDIAN) + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg + 1], s, + reg_names[gparg + 1], reg_names[fparg]); + else + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg], s, + reg_names[gparg + 1], reg_names[fparg + 1]); ++gparg; ++fparg; } @@ -7777,12 +7785,24 @@ build_mips16_call_stub (retval, fnmem, arg_size, fp_code) reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); else { - fprintf (asm_out_file, "\tmfc1\t%s,%s\n", - reg_names[GP_REG_FIRST + 2], - reg_names[FP_REG_FIRST + 1]); - fprintf (asm_out_file, "\tmfc1\t%s,%s\n", - reg_names[GP_REG_FIRST + 3], - reg_names[FP_REG_FIRST + 0]); + if (TARGET_BIG_ENDIAN) + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 1]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 0]); + } + else + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 0]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 1]); + } } fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]); /* As above, we can't fill the delay slot. */ diff --git a/gcc/config/mips/mips16.S b/gcc/config/mips/mips16.S index f5af9e7..f21f10f 100644 --- a/gcc/config/mips/mips16.S +++ b/gcc/config/mips/mips16.S @@ -330,7 +330,7 @@ STARTFN (NAME); \ STARTFN (NAME); \ LDDBL1; \ LDDBL2; \ - OPCODE $f12,$f14; \ + OPCODE $f14,$f12; \ li $2,TRUE; \ bc1t 1f; \ li $2,FALSE; \ |