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authorKazu Hirata <kazu@cs.umass.edu>2004-01-10 22:34:13 +0000
committerKazu Hirata <kazu@gcc.gnu.org>2004-01-10 22:34:13 +0000
commita2ab189d04027ac47edefaba4e3ab6d4a93a0891 (patch)
tree180fdd53b28789ea7760e012a95e48f46c5fe61f /gcc
parent162fd675e5647239cc88413481f23b87e688a756 (diff)
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m32r.md: Use define_constants for unspec and unspec_volatile.
* config/m32r/m32r.md: Use define_constants for unspec and unspec_volatile. From-SVN: r75656
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/m32r/m32r.md43
2 files changed, 30 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a5560ca..adf35bb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-10 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/m32r/m32r.md: Use define_constants for unspec and
+ unspec_volatile.
+
2004-01-10 Jan Hubicka <jh@suse.cz>
PR opt/11635
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 7d235f9..78d9df1 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -19,13 +19,19 @@
;; Boston, MA 02111-1307, USA.
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; unspec usage
-;; 0 - blockage
-;; 1 - flush_icache
-;; 2 - load_sda_base
-;; 3 - setting carry in addx/subx instructions.
+;; UNSPEC_VOLATILE usage
+(define_constants
+ [(UNSPECV_BLOCKAGE 0)
+ (UNSPECV_FLUSH_ICACHE 1)])
+
+;; UNSPEC usage
+(define_constants
+ [(UNSPEC_LOAD_SDA_BASE 2)
+ (UNSPEC_SET_CBIT 3)
+ (UNSPEC_PIC_LOAD_ADDR 4)
+ (UNSPEC_GET_PC 5)])
+
;; Insn type. Used to default other attribute values.
(define_attr "type"
"int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
@@ -564,7 +570,7 @@
(define_expand "movsi_sda"
[(set (match_dup 2)
- (unspec [(const_int 0)] 2))
+ (unspec [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
(set (match_operand:SI 0 "register_operand" "")
(lo_sum:SI (match_dup 2)
(match_operand:SI 1 "small_data_operand" "")))]
@@ -579,7 +585,7 @@
(define_insn "*load_sda_base"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(const_int 0)] 2))]
+ (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
""
"ld24 %0,#_SDA_BASE_"
[(set_attr "type" "int4")
@@ -921,13 +927,13 @@
(plus:SI (match_dup 5)
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))])
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
(parallel [(set (match_dup 6)
(plus:SI (match_dup 6)
(plus:SI (match_dup 7)
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))])]
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
"
{
operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
@@ -951,7 +957,7 @@
(plus:SI (match_operand:SI 2 "register_operand" "r")
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))]
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
""
"addx %0,%2"
[(set_attr "type" "int2")
@@ -991,13 +997,13 @@
(minus:SI (match_dup 5)
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))])
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
(parallel [(set (match_dup 6)
(minus:SI (match_dup 6)
(minus:SI (match_dup 7)
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))])]
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
"
{
operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
@@ -1012,7 +1018,7 @@
(minus:SI (match_operand:SI 2 "register_operand" "r")
(ne:SI (reg:CC 17) (const_int 0)))))
(set (reg:CC 17)
- (unspec:CC [(const_int 0)] 3))]
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
""
"subx %0,%2"
[(set_attr "type" "int2")
@@ -2494,14 +2500,15 @@
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
"")
;; Special pattern to flush the icache.
(define_insn "flush_icache"
- [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 1)
+ [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
+ UNSPECV_FLUSH_ICACHE)
(match_operand 1 "" "")
(clobber (reg:SI 17))]
""
@@ -2700,7 +2707,7 @@
(define_insn "pic_load_addr"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand 1 "" "")] 4))]
+ (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
"flag_pic"
"ld24 %0,%#%1"
[(set_attr "type" "int4")])
@@ -2710,7 +2717,7 @@
(define_insn "get_pc"
[(clobber (reg:SI 14))
(set (match_operand 0 "register_operand" "=r")
- (unspec [(match_operand 1 "" "")] 5))
+ (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
(use (match_operand:SI 2 "immediate_operand" ""))]
"flag_pic"
"*