s390.c (regclass_map): Put reg 33 (cc) to CC_REGS group.

2004-11-01  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/s390/s390.c (regclass_map): Put reg 33 (cc) to CC_REGS group.
	(s390_secondary_input_reload_class)
	(s390_secondary_output_reload_class): Use GENERAL_REGS to reload a cc
	register.
	(s390_expand_cmpmem): Enable cmpmem implementation.
	* config/s390/s390.h (reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
	Added three new classes: CC_REGS, ADDR_CC_REGS, GENERAL_CC_REGS.
	(REG_CLASS_FROM_LETTER): New constraint 'c' added.
	* config/s390/s390.md ("movcc"): New insn pattern.
	* doc/md.texi: Document 'c' constraint for s390.

From-SVN: r89953

5 files changed, 56 insertions, 13 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 067be29..84ca204 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2004-11-01  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+	* config/s390/s390.c (regclass_map): Put reg 33 (cc) to CC_REGS group.
+	(s390_secondary_input_reload_class)
+	(s390_secondary_output_reload_class): Use GENERAL_REGS to reload a cc
+	register.
+	(s390_expand_cmpmem): Enable cmpmem implementation.
+	* config/s390/s390.h (reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
+	Added three new classes: CC_REGS, ADDR_CC_REGS, GENERAL_CC_REGS.
+	(REG_CLASS_FROM_LETTER): New constraint 'c' added.
+	* config/s390/s390.md ("movcc"): New insn pattern.
+	* doc/md.texi: Document 'c' constraint for s390.
+
 2004-11-01  Nathan Sidwell  <nathan@codesourcery.com>
 
 	PR c++/18064
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 89e1cb1..d56624c 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1355,7 +1355,7 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
-  ADDR_REGS,    NO_REGS,   ADDR_REGS, ADDR_REGS
+  ADDR_REGS,    CC_REGS,   ADDR_REGS, ADDR_REGS
 };
 
 /* Return attribute type of insn.  */
@@ -2276,6 +2276,9 @@ s390_secondary_input_reload_class (enum reg_class class ATTRIBUTE_UNUSED,
   if (s390_plus_operand (in, mode))
     return ADDR_REGS;
 
+  if (GET_MODE_CLASS (mode) == MODE_CC)
+    return GENERAL_REGS;
+
   return NO_REGS;
 }
 
@@ -2297,6 +2300,9 @@ s390_secondary_output_reload_class (enum reg_class class,
       && !s_operand (out, VOIDmode))
     return ADDR_REGS;
 
+  if (GET_MODE_CLASS (mode) == MODE_CC)
+    return GENERAL_REGS;
+
   return NO_REGS;
 }
 
@@ -3579,16 +3585,11 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
       else
         emit_move_insn (target, const0_rtx);
     }
-
-  else /* if (TARGET_MVCLE) */
+  else if (TARGET_MVCLE)
     {
       emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
       emit_move_insn (target, result);
     }
-
-#if 0
-  /* Deactivate for now as profile code cannot cope with
-     CC being live across basic block boundaries.  */
   else
     {
       rtx addr0, addr1, count, blocks, temp;
@@ -3656,7 +3657,6 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
 
       emit_move_insn (target, result);
     }
-#endif
 }
 
 
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 2217e83..013fd93 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -448,8 +448,11 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
 
 /* We use the following register classes:
    GENERAL_REGS     All general purpose registers
+   CC_REGS          Contains only the condition code register
    ADDR_REGS        All general purpose registers except %r0
                     (These registers can be used in address generation)
+   ADDR_CC_REGS     Union of ADDR_REGS and CC_REGS
+   GENERAL_CC_REGS  Union of GENERAL_REGS and CC_REGS
    FP_REGS          All floating point registers
 
    GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
@@ -464,22 +467,26 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
 
 enum reg_class
 {
-  NO_REGS, ADDR_REGS, GENERAL_REGS,
+  NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, 
+  ADDR_CC_REGS, GENERAL_CC_REGS, 
   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
   ALL_REGS, LIM_REG_CLASSES
 };
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
-#define REG_CLASS_NAMES                                                 \
-{ "NO_REGS", "ADDR_REGS", "GENERAL_REGS", 				\
-  "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
+#define REG_CLASS_NAMES                                                        \
+{ "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ADDR_CC_REGS",           \
+  "GENERAL_CC_REGS", "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
 
 /* Class -> register mapping.  */
 #define REG_CLASS_CONTENTS \
 {				       			\
   { 0x00000000, 0x00000000 },	/* NO_REGS */		\
+  { 0x00000000, 0x00000002 },	/* CC_REGS */		\
   { 0x0000fffe, 0x0000000d },	/* ADDR_REGS */		\
   { 0x0000ffff, 0x0000000d },	/* GENERAL_REGS */	\
+  { 0x0000fffe, 0x0000000f },	/* ADDR_CC_REGS */	\
+  { 0x0000ffff, 0x0000000f },	/* GENERAL_CC_REGS */	\
   { 0xffff0000, 0x00000000 },	/* FP_REGS */		\
   { 0xfffffffe, 0x0000000d },	/* ADDR_FP_REGS */	\
   { 0xffffffff, 0x0000000d },	/* GENERAL_FP_REGS */	\
@@ -535,7 +542,8 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 #define REG_CLASS_FROM_LETTER(C)                                        \
   ((C) == 'a' ? ADDR_REGS :                                             \
    (C) == 'd' ? GENERAL_REGS :                                          \
-   (C) == 'f' ? FP_REGS : NO_REGS)
+   (C) == 'f' ? FP_REGS :                                               \
+   (C) == 'c' ? CC_REGS : NO_REGS)
 
 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR)                          \
   s390_const_ok_for_constraint_p ((VALUE), (C), (STR))
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 6c29917..0368466 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -25,6 +25,7 @@
 ;; Special constraints for s/390 machine description:
 ;;
 ;;    a -- Any address register from 1 to 15.
+;;    c -- Condition code register 33.
 ;;    d -- Any register from 0 to 15.
 ;;    I -- An 8-bit constant (0..255).
 ;;    J -- A 12-bit constant (0..4095).
@@ -1452,6 +1453,24 @@
    (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
 
 ;
+; movcc instruction pattern
+;
+
+(define_insn "movcc"
+  [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
+	(match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
+  ""
+  "@
+   lr\t%0,%1
+   tmh\t%1,12288
+   ipm\t%0
+   st\t%0,%1
+   sty\t%0,%1
+   l\t%1,%0
+   ly\t%1,%0"
+  [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")])
+
+;
 ; Block move (MVC) patterns.
 ;
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 23b5e52..5b5b03e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2458,6 +2458,9 @@ Symbolic address
 @item a
 Address register (general purpose register except r0)
 
+@item c
+Condition code register
+
 @item d
 Data register (arbitrary general purpose register)