sparc.c (fp_sethi_p): Test !SPARC_SIMM13_P and remove redundant test.

	* config/sparc/sparc.c (fp_sethi_p): Test !SPARC_SIMM13_P and
	remove redundant test.
	(fp_mov_p): Accept 0.
	(fp_high_losum_p): Remove redundant test.
	* config/sparc/predicates.md (const_high_operand): Explicitly test
	(not small_int_operand).
	(fp_const_high_losum_operand): New.
	* config/sparc/sparc.md (movsi_insn): Do not emit 'clr'.  Reorder.
	(movdi_insn_sp32_v9): Use canonical predicates.
	(movdi_insn_sp32): Test !TARGET_V9 instead of !TARGET_ARCH64.
	(movdi_insn_sp64_novis): Delete.
	(movdi_insn_sp64_vis): Rename into movdi_insn_sp64.
	(movsf_insn_novis): Delete.
	(movsf_insn_vis): Rename into movsf_insn.
	(movsf_no_f_insn): Rename into movsf_insn_no_fpu.
	(movsf_lo_sum): Use fp_const_high_losum_operand.
	(movsf_high): Likewise.
	(movsf_high_losum splitter): Likewise.
	(mov<V32:mode> expander): Use register_or_zero_operand.
	(mov<V64:mode> expander): Likewise.
	(movdf_insn_sp32): Use register_or_zero_operand.
	(movdf_no_e_insn_sp32): Use register_or_zero_operand.
	Rename into movdf_insn_sp32_no_fpu.
	(movdf_no_e_insn_v9_sp32): Use register_or_zero_operand.
	Rename into movdf_insn_sp32_v9_no_fpu.
	(movdf_insn_v9only_novis): Delete.
	(movdf_insn_v9only_vis): Rename into movdf_insn_sp32_v9.
	(movdf_insn_sp64_novis): Delete.
	(movdf_insn_sp64_vis): Rename into movdf_insn_sp64.
	(movdf_no_e_insn_sp64): Use register_or_zero_operand.
	Rename into movdf_insn_sp64_no_fpu.
	(movtf expander): Use register_or_zero_operand.
	(movtf_insn_sp32): Delete.
	(movtf_insn_vis_sp32): Use register_or_zero_operand.
	Rename into movtf_insn_sp32.
	(movtf_no_e_insn_sp32): Use register_or_zero_operand.
	Rename into movtf_insn_sp32_no_fpu.
	(movtf_insn_hq_sp64): Delete.
	(movtf_insn_hq_vis_sp64): Use register_or_zero_operand.
	Rename into movtf_insn_sp64_hq.
	(movtf_insn_sp64): Delete.
	(movtf_insn_vis_sp64): Use register_or_zero_operand.
	Rename into movtf_insn_sp64.
	(movtf_no_e_insn_sp64): Use register_or_zero_operand.
	Rename into movtf_insn_sp64_no_fpu.

From-SVN: r99506

4 files changed, 146 insertions, 291 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 356e328..847acee 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,51 @@
+2005-05-10  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* config/sparc/sparc.c (fp_sethi_p): Test !SPARC_SIMM13_P and
+	remove redundant test.
+	(fp_mov_p): Accept 0.
+	(fp_high_losum_p): Remove redundant test.
+	* config/sparc/predicates.md (const_high_operand): Explicitly test
+	(not small_int_operand).
+	(fp_const_high_losum_operand): New.
+	* config/sparc/sparc.md (movsi_insn): Do not emit 'clr'.  Reorder.
+	(movdi_insn_sp32_v9): Use canonical predicates.
+	(movdi_insn_sp32): Test !TARGET_V9 instead of !TARGET_ARCH64.
+	(movdi_insn_sp64_novis): Delete.
+	(movdi_insn_sp64_vis): Rename into movdi_insn_sp64.
+	(movsf_insn_novis): Delete.
+	(movsf_insn_vis): Rename into movsf_insn.
+	(movsf_no_f_insn): Rename into movsf_insn_no_fpu.
+	(movsf_lo_sum): Use fp_const_high_losum_operand.
+	(movsf_high): Likewise.
+	(movsf_high_losum splitter): Likewise.
+	(mov<V32:mode> expander): Use register_or_zero_operand.
+	(mov<V64:mode> expander): Likewise.
+	(movdf_insn_sp32): Use register_or_zero_operand.
+	(movdf_no_e_insn_sp32): Use register_or_zero_operand.
+	Rename into movdf_insn_sp32_no_fpu.
+	(movdf_no_e_insn_v9_sp32): Use register_or_zero_operand.
+	Rename into movdf_insn_sp32_v9_no_fpu.
+	(movdf_insn_v9only_novis): Delete.
+	(movdf_insn_v9only_vis): Rename into movdf_insn_sp32_v9.
+	(movdf_insn_sp64_novis): Delete.
+	(movdf_insn_sp64_vis): Rename into movdf_insn_sp64.
+	(movdf_no_e_insn_sp64): Use register_or_zero_operand. 
+	Rename into movdf_insn_sp64_no_fpu.
+	(movtf expander): Use register_or_zero_operand.
+	(movtf_insn_sp32): Delete.
+	(movtf_insn_vis_sp32): Use register_or_zero_operand.
+	Rename into movtf_insn_sp32.
+	(movtf_no_e_insn_sp32): Use register_or_zero_operand.
+	Rename into movtf_insn_sp32_no_fpu.
+	(movtf_insn_hq_sp64): Delete.
+	(movtf_insn_hq_vis_sp64): Use register_or_zero_operand.
+	Rename into movtf_insn_sp64_hq.
+	(movtf_insn_sp64): Delete.
+	(movtf_insn_vis_sp64): Use register_or_zero_operand.
+	Rename into movtf_insn_sp64.
+	(movtf_no_e_insn_sp64): Use register_or_zero_operand.
+	Rename into movtf_insn_sp64_no_fpu.
+
 2005-05-10  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* config/stormy16/stormy16.c (xstormy16_emit_cbranch): Use
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 58f0bb7..b56ae65 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -65,7 +65,7 @@
 ;; The first test avoids emitting sethi to load zero for example.
 (define_predicate "const_high_operand"
   (and (match_code "const_int")
-       (and (match_test "INTVAL (op) & ~(HOST_WIDE_INT)0x3ff")
+       (and (not (match_operand 0 "small_int_operand"))
             (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
 
 ;; Return true if OP is a constant whose 1's complement can be loaded by the
@@ -75,6 +75,16 @@
        (and (not (match_operand 0 "small_int_operand"))
             (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))"))))
 
+;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum
+;; pair of instructions.
+(define_predicate "fp_const_high_losum_operand"
+  (match_operand 0 "const_double_operand")
+{
+  gcc_assert (mode == SFmode);
+  return fp_high_losum_p (op);
+})
+
+
 ;; Predicates for symbolic constants.
 
 ;; Return true if OP is either a symbol reference or a sum of a symbol
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 94ef74d..6715437 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -818,12 +818,8 @@ fp_sethi_p (rtx op)
       long i;
 
       REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      if (REAL_VALUES_EQUAL (r, dconst0) &&
-	  ! REAL_VALUE_MINUS_ZERO (r))
-	return 0;
       REAL_VALUE_TO_TARGET_SINGLE (r, i);
-      if (SPARC_SETHI_P (i))
-	return 1;
+      return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
     }
 
   return 0;
@@ -842,12 +838,8 @@ fp_mov_p (rtx op)
       long i;
 
       REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      if (REAL_VALUES_EQUAL (r, dconst0) &&
-	  ! REAL_VALUE_MINUS_ZERO (r))
-	return 0;
       REAL_VALUE_TO_TARGET_SINGLE (r, i);
-      if (SPARC_SIMM13_P (i))
-	return 1;
+      return SPARC_SIMM13_P (i);
     }
 
   return 0;
@@ -869,13 +861,8 @@ fp_high_losum_p (rtx op)
       long i;
 
       REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      if (REAL_VALUES_EQUAL (r, dconst0) &&
-	  ! REAL_VALUE_MINUS_ZERO (r))
-	return 0;
       REAL_VALUE_TO_TARGET_SINGLE (r, i);
-      if (! SPARC_SETHI_P (i)
-          && ! SPARC_SIMM13_P (i))
-	return 1;
+      return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
     }
 
   return 0;
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 2078c3a..1e6ba93 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1938,21 +1938,20 @@
 })
 
 (define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
-	(match_operand:SI 1 "input_operand"   "rI,!f,K,J,m,!m,rJ,!f,J"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d")
+	(match_operand:SI 1 "input_operand"   "rI,K,m,rJ,f,m,f,J"))]
   "(register_operand (operands[0], SImode)
     || register_or_zero_operand (operands[1], SImode))"
   "@
    mov\t%1, %0
-   fmovs\t%1, %0
    sethi\t%%hi(%a1), %0
-   clr\t%0
-   ld\t%1, %0
    ld\t%1, %0
    st\t%r1, %0
+   fmovs\t%1, %0
+   ld\t%1, %0
    st\t%1, %0
    fzeros\t%0"
-  [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fga")])
+  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")])
 
 (define_insn "*movsi_lo_sum"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2127,8 +2126,10 @@
 					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
         (match_operand:DI 1 "input_operand"
 					" J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
-  "! TARGET_ARCH64 && TARGET_V9
-   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+  "! TARGET_ARCH64
+   && TARGET_V9
+   && (register_operand (operands[0], DImode)
+       || register_or_zero_operand (operands[1], DImode))"
   "@
    stx\t%%g0, %0
    #
@@ -2154,7 +2155,7 @@
 				"=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
         (match_operand:DI 1 "input_operand"
 				" J,U,T,r,o,i,r, f, T, o, f, f"))]
-  "! TARGET_ARCH64
+  "! TARGET_V9
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   "@
@@ -2173,46 +2174,27 @@
   [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
    (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
 
-(define_insn "*movdi_insn_sp64_novis"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
-        (match_operand:DI 1 "input_operand"   "rI,N,J,m,rJ,e,W,e"))]
-  "TARGET_ARCH64 && ! TARGET_VIS
-   && (register_operand (operands[0], DImode)
-       || register_or_zero_operand (operands[1], DImode))"
-  "@
-   mov\t%1, %0
-   sethi\t%%hi(%a1), %0
-   clr\t%0
-   ldx\t%1, %0
-   stx\t%r1, %0
-   fmovd\t%1, %0
-   ldd\t%1, %0
-   std\t%1, %0"
-  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
-   (set_attr "fptype" "*,*,*,*,*,double,*,*")])
-
 ;; We don't define V1SI because SI should work just fine.
 (define_mode_macro V64 [DF V2SI V4HI V8QI])
 (define_mode_macro V32 [SF V2HI V4QI])
 
-(define_insn "*movdi_insn_sp64_vis"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
-        (match_operand:DI 1 "input_operand"   "rI,N,J,m,rJ,e,W,e,J"))]
-  "TARGET_ARCH64 && TARGET_VIS &&
-   (register_operand (operands[0], DImode)
-    || register_or_zero_operand (operands[1], DImode))"
+(define_insn "*movdi_insn_sp64"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b")
+        (match_operand:DI 1 "input_operand"   "rI,N,m,rJ,e,W,e,J"))]
+  "TARGET_ARCH64
+   && (register_operand (operands[0], DImode)
+       || register_or_zero_operand (operands[1], DImode))"
   "@
    mov\t%1, %0
    sethi\t%%hi(%a1), %0
-   clr\t%0
    ldx\t%1, %0
    stx\t%r1, %0
    fmovd\t%1, %0
    ldd\t%1, %0
    std\t%1, %0
    fzero\t%0"
-  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fga")
-   (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
+  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")
+   (set_attr "fptype" "*,*,*,*,double,*,*,double")])
 
 (define_expand "movdi_pic_label_ref"
   [(set (match_dup 3) (high:DI
@@ -2566,16 +2548,16 @@
   emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
   DONE;
 })
-
-;; Floating point move insns
 
-(define_insn "*movsf_insn_novis"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
-	(match_operand:SF 1 "input_operand"         "f,G,Q,*rR,S,m,m,f,*rG"))]
-  "(TARGET_FPU && ! TARGET_VIS)
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode)
-       || const_zero_operand (operands[1], SFmode))"
+
+;; Floating point and vector move instructions
+
+(define_insn "*movsf_insn"
+  [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,*r,f,m,m")
+	(match_operand:V32 1 "input_operand"        "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
+  "TARGET_FPU
+   && (register_operand (operands[0], <V32:MODE>mode)
+       || register_or_zero_operand (operands[1], <V32:MODE>mode))"
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
       && (which_alternative == 2
@@ -2593,90 +2575,42 @@
   switch (which_alternative)
     {
     case 0:
-      return "fmovs\t%1, %0";
+      return "fzeros\t%0";
     case 1:
-      return "clr\t%0";
-    case 2:
-      return "sethi\t%%hi(%a1), %0";
-    case 3:
-      return "mov\t%1, %0";
-    case 4:
-      return "#";
-    case 5:
-    case 6:
-      return "ld\t%1, %0";
-    case 7:
-    case 8:
-      return "st\t%r1, %0";
-    default:
-      gcc_unreachable ();
-    }
-}
-  [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
-
-(define_insn "*movsf_insn_vis"
-  [(set (match_operand:V32 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
-	(match_operand:V32 1 "input_operand"         "f,GY,GY,Q,*rR,S,m,m,f,*rGY"))]
-  "(TARGET_FPU && TARGET_VIS)
-   && (register_operand (operands[0], <V32:MODE>mode)
-       || register_operand (operands[1], <V32:MODE>mode)
-       || const_zero_operand (operands[1], <V32:MODE>mode))"
-{
-  if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && (which_alternative == 3
-          || which_alternative == 4
-          || which_alternative == 5))
-    {
-      REAL_VALUE_TYPE r;
-      long i;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-      REAL_VALUE_TO_TARGET_SINGLE (r, i);
-      operands[1] = GEN_INT (i);
-    }
-
-  switch (which_alternative)
-    {
-    case 0:
       return "fmovs\t%1, %0";
-    case 1:
-      return "fzeros\t%0";
     case 2:
-      return "clr\t%0";
+      return "mov\t%1, %0";
     case 3:
       return "sethi\t%%hi(%a1), %0";
     case 4:
-      return "mov\t%1, %0";
-    case 5:
       return "#";
+    case 5:
     case 6:
-    case 7:
       return "ld\t%1, %0";
+    case 7:
     case 8:
-    case 9:
       return "st\t%r1, %0";
     default:
       gcc_unreachable ();
     }
 }
-  [(set_attr "type" "fpmove,fga,*,*,*,*,load,fpload,fpstore,store")])
+  [(set_attr "type" "fga,fpmove,*,*,*,load,fpload,fpstore,store")])
 
 ;; Exactly the same as above, except that all `f' cases are deleted.
 ;; This is necessary to prevent reload from ever trying to use a `f' reg
 ;; when -mno-fpu.
 
-(define_insn "*movsf_no_f_insn"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,m")
-	(match_operand:SF 1 "input_operand"    "G,Q,rR,S,m,rG"))]
+(define_insn "*movsf_insn_no_fpu"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
+	(match_operand:SF 1 "input_operand"    "rR,Q,S,m,rG"))]
   "! TARGET_FPU
    && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode)
-       || const_zero_operand (operands[1], SFmode))"
+       || register_or_zero_operand (operands[1], SFmode))"
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && (which_alternative == 1
-          || which_alternative == 2
-          || which_alternative == 3))
+      && (which_alternative == 0
+          || which_alternative == 1
+          || which_alternative == 2))
     {
       REAL_VALUE_TYPE r;
       long i;
@@ -2689,30 +2623,28 @@
   switch (which_alternative)
     {
     case 0:
-      return "clr\t%0";
+      return "mov\t%1, %0";
     case 1:
       return "sethi\t%%hi(%a1), %0";
     case 2:
-      return "mov\t%1, %0";
-    case 3:
       return "#";
-    case 4:
+    case 3:
       return "ld\t%1, %0";
-    case 5:
+    case 4:
       return "st\t%r1, %0";
     default:
       gcc_unreachable ();
     }
 }
-  [(set_attr "type" "*,*,*,*,load,store")])
+  [(set_attr "type" "*,*,*,load,store")])
 
 ;; The following 3 patterns build SFmode constants in integer registers.
 
 (define_insn "*movsf_lo_sum"
   [(set (match_operand:SF 0 "register_operand" "=r")
         (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
-                   (match_operand:SF 2 "const_double_operand" "S")))]
-  "fp_high_losum_p (operands[2])"
+                   (match_operand:SF 2 "fp_const_high_losum_operand" "S")))]
+  ""
 {
   REAL_VALUE_TYPE r;
   long i;
@@ -2725,8 +2657,8 @@
 
 (define_insn "*movsf_high"
   [(set (match_operand:SF 0 "register_operand" "=r")
-        (high:SF (match_operand:SF 1 "const_double_operand" "S")))]
-  "fp_high_losum_p (operands[1])"
+        (high:SF (match_operand:SF 1 "fp_const_high_losum_operand" "S")))]
+  ""
 {
   REAL_VALUE_TYPE r;
   long i;
@@ -2739,10 +2671,8 @@
 
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
-        (match_operand:SF 1 "const_double_operand" ""))]
-  "fp_high_losum_p (operands[1])
-   && (GET_CODE (operands[0]) == REG
-       && REGNO (operands[0]) < 32)"
+        (match_operand:SF 1 "fp_const_high_losum_operand" ""))]
+  "REG_P (operands[0]) && REGNO (operands[0]) < 32"
   [(set (match_dup 0) (high:SF (match_dup 1)))
    (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
 
@@ -2778,8 +2708,7 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], <V32:MODE>mode)
-	  || const_zero_operand (operands[1], <V32:MODE>mode))
+      if (register_or_zero_operand (operands[1], <V32:MODE>mode))
 	goto movsf_is_ok;
 
       if (! reload_in_progress)
@@ -2842,8 +2771,7 @@
   /* Handle MEM cases first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], <V64:MODE>mode)
-	  || const_zero_operand (operands[1], <V64:MODE>mode))
+      if (register_or_zero_operand (operands[1], <V64:MODE>mode))
 	goto movdf_is_ok;
 
       if (! reload_in_progress)
@@ -2881,8 +2809,7 @@
   "TARGET_FPU
    && ! TARGET_V9
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
+       || register_or_zero_operand (operands[1], DFmode))"
   "@
   ldd\t%1, %0
   std\t%1, %0
@@ -2897,15 +2824,13 @@
  [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
   (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
 
-(define_insn "*movdf_no_e_insn_sp32"
+(define_insn "*movdf_insn_sp32_no_fpu"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
 	(match_operand:DF 1 "input_operand"    "T,U,G,ro,r"))]
   "! TARGET_FPU
    && ! TARGET_V9
-   && ! TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
+       || register_or_zero_operand (operands[1], DFmode))"
   "@
   ldd\t%1, %0
   std\t%1, %0
@@ -2915,15 +2840,14 @@
   [(set_attr "type" "load,store,*,*,*")
    (set_attr "length" "*,*,2,2,2")])
 
-(define_insn "*movdf_no_e_insn_v9_sp32"
+(define_insn "*movdf_insn_sp32_v9_no_fpu"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
 	(match_operand:DF 1 "input_operand"    "T,U,G,ro,rG"))]
   "! TARGET_FPU
    && TARGET_V9
    && ! TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
+       || register_or_zero_operand (operands[1], DFmode))"
   "@
   ldd\t%1, %0
   std\t%1, %0
@@ -2933,43 +2857,15 @@
   [(set_attr "type" "load,store,store,*,*")
    (set_attr "length" "*,*,*,2,2")])
 
-;; We have available v9 double floats but not 64-bit
-;; integer registers and no VIS.
-(define_insn "*movdf_insn_v9only_novis"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
-        (match_operand:DF 1 "input_operand"    "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
-  "TARGET_FPU
-   && TARGET_V9
-   && ! TARGET_VIS
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
-  "@
-  fmovd\t%1, %0
-  ldd\t%1, %0
-  stx\t%r1, %0
-  std\t%1, %0
-  ldd\t%1, %0
-  std\t%1, %0
-  #
-  #
-  #"
-  [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
-   (set_attr "length" "*,*,*,*,*,*,2,2,2")
-   (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
-
-;; We have available v9 double floats but not 64-bit
-;; integer registers but we have VIS.
-(define_insn "*movdf_insn_v9only_vis"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
+;; We have available v9 double floats but not 64-bit integer registers.
+(define_insn "*movdf_insn_sp32_v9"
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
         (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYF,*rGYf"))]
   "TARGET_FPU
-   && TARGET_VIS
+   && TARGET_V9
    && ! TARGET_ARCH64
    && (register_operand (operands[0], <V64:MODE>mode)
-       || register_operand (operands[1], <V64:MODE>mode)
-       || const_zero_operand (operands[1], <V64:MODE>mode))"
+       || register_or_zero_operand (operands[1], <V64:MODE>mode))"
   "@
   fzero\t%0
   fmovd\t%1, %0
@@ -2985,40 +2881,14 @@
    (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
    (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
 
-;; We have available both v9 double floats and 64-bit
-;; integer registers. No VIS though.
-(define_insn "*movdf_insn_sp64_novis"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r")
-        (match_operand:DF 1 "input_operand"    "e,W#F,e,*rG,m,*rG,F"))]
-  "TARGET_FPU
-   && ! TARGET_VIS
-   && TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
-  "@
-  fmovd\t%1, %0
-  ldd\t%1, %0
-  std\t%1, %0
-  mov\t%r1, %0
-  ldx\t%1, %0
-  stx\t%r1, %0
-  #"
-  [(set_attr "type" "fpmove,load,store,*,load,store,*")
-   (set_attr "length" "*,*,*,*,*,*,2")
-   (set_attr "fptype" "double,*,*,*,*,*,*")])
-
-;; We have available both v9 double floats and 64-bit
-;; integer registers. And we have VIS.
-(define_insn "*movdf_insn_sp64_vis"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
+;; We have available both v9 double floats and 64-bit integer registers.
+(define_insn "*movdf_insn_sp64"
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
         (match_operand:V64 1 "input_operand"    "GY,e,W#F,e,*rGY,m,*rGY,F"))]
   "TARGET_FPU
-   && TARGET_VIS
    && TARGET_ARCH64
    && (register_operand (operands[0], <V64:MODE>mode)
-       || register_operand (operands[1], <V64:MODE>mode)
-       || const_zero_operand (operands[1], <V64:MODE>mode))"
+       || register_or_zero_operand (operands[1], <V64:MODE>mode))"
   "@
   fzero\t%0
   fmovd\t%1, %0
@@ -3032,14 +2902,13 @@
    (set_attr "length" "*,*,*,*,*,*,*,2")
    (set_attr "fptype" "double,double,*,*,*,*,*,*")])
 
-(define_insn "*movdf_no_e_insn_sp64"
+(define_insn "*movdf_insn_sp64_no_fpu"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
         (match_operand:DF 1 "input_operand"    "r,m,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || const_zero_operand (operands[1], DFmode))"
+       || register_or_zero_operand (operands[1], DFmode))"
   "@
   mov\t%1, %0
   ldx\t%1, %0
@@ -3293,8 +3162,7 @@
      full 16-byte alignment for quads.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      if (register_operand (operands[1], TFmode)
-	  || const_zero_operand (operands[1], TFmode))
+      if (register_or_zero_operand (operands[1], TFmode))
 	goto movtf_is_ok;
 
       if (! reload_in_progress)
@@ -3325,29 +3193,13 @@
   ;
 })
 
-;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
-;; we must split them all.  :-(
 (define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
-	(match_operand:TF 1 "input_operand"    "oe,GeUr,o,roG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
+	(match_operand:TF 1 "input_operand"    "G,oe,GeUr,o,roG"))]
   "TARGET_FPU
-   && ! TARGET_VIS
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "4")])
-
-(define_insn "*movtf_insn_vis_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
-	(match_operand:TF 1 "input_operand"    "Goe,GeUr,o,roG"))]
-  "TARGET_FPU
-   && TARGET_VIS
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
+       || register_or_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "4")])
 
@@ -3355,94 +3207,52 @@
 ;; This is necessary to prevent reload from ever trying to use a `e' reg
 ;; when -mno-fpu.
 
-(define_insn "*movtf_no_e_insn_sp32"
+(define_insn "*movtf_insn_sp32_no_fpu"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
 	(match_operand:TF 1 "input_operand"    "G,o,U,roG,r"))]
   "! TARGET_FPU
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
+       || register_or_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "4")])
 
-;; Now handle the float reg cases directly when arch64,
-;; hard_quad, and proper reg number alignment are all true.
-(define_insn "*movtf_insn_hq_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
-        (match_operand:TF 1 "input_operand"    "e,m,e,Gr,roG"))]
+(define_insn "*movtf_insn_sp64_hq"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
+        (match_operand:TF 1 "input_operand"    "G,e,m,e,rG,roG"))]
   "TARGET_FPU
-   && ! TARGET_VIS
    && TARGET_ARCH64
    && TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
+       || register_or_zero_operand (operands[1], TFmode))"
   "@
-  fmovq\t%1, %0
-  ldq\t%1, %0
-  stq\t%1, %0
   #
-  #"
-  [(set_attr "type" "fpmove,fpload,fpstore,*,*")
-   (set_attr "length" "*,*,*,2,2")])
-
-(define_insn "*movtf_insn_hq_vis_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
-        (match_operand:TF 1 "input_operand"    "e,m,e,G,roG,r"))]
-  "TARGET_FPU
-   && TARGET_VIS
-   && TARGET_ARCH64
-   && TARGET_HARD_QUAD
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
-  "@
   fmovq\t%1, %0
   ldq\t%1, %0
   stq\t%1, %0
   #
-  #
   #"
-  [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
-   (set_attr "length" "*,*,*,2,2,2")])
+  [(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
+   (set_attr "length" "2,*,*,*,2,2")])
 
-;; Now we allow the integer register cases even when
-;; only arch64 is true.
 (define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
-        (match_operand:TF 1 "input_operand"    "oe,Ger,orG"))]
-  "TARGET_FPU
-   && ! TARGET_VIS
-   && TARGET_ARCH64
-   && ! TARGET_HARD_QUAD
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_insn "*movtf_insn_vis_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
-        (match_operand:TF 1 "input_operand"    "Goe,Ger,orG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
+        (match_operand:TF 1 "input_operand"    "G,oe,Ger,roG"))]
   "TARGET_FPU
-   && TARGET_VIS
    && TARGET_ARCH64
    && ! TARGET_HARD_QUAD
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
+       || register_or_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "2")])
 
-(define_insn "*movtf_no_e_insn_sp64"
+(define_insn "*movtf_insn_sp64_no_fpu"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
         (match_operand:TF 1 "input_operand"    "orG,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode)
-       || const_zero_operand (operands[1], TFmode))"
+       || register_or_zero_operand (operands[1], TFmode))"
   "#"
   [(set_attr "length" "2")])