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| author | Uros Bizjak <uros@gcc.gnu.org> | 2016-04-27 20:10:02 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-04-27 20:10:02 +0200 |
| commit | 98544adc26c0f956ecf63495749f029e3943bc31 (patch) | |
| tree | 1f9ab2032cfeea3be2c9bb3b146ba2e1f8f1af2f /gcc | |
| parent | b55b11bb7a9aceb8c7ffda6c194347ec6c1556e5 (diff) | |
| download | gcc-98544adc26c0f956ecf63495749f029e3943bc31.zip gcc-98544adc26c0f956ecf63495749f029e3943bc31.tar.gz gcc-98544adc26c0f956ecf63495749f029e3943bc31.tar.bz2 | |
i386.c (ix86_spill_class): Enable for TARGET_SSE2 when inter-unit moves to/from vector registers are enabled.
* config/i386/i386.c (ix86_spill_class): Enable for TARGET_SSE2 when
inter-unit moves to/from vector registers are enabled. Do not disable
for TARGET_MMX.
From-SVN: r235523
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 19 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 7 |
2 files changed, 20 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6302382..cac640e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-04-27 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_spill_class): Enable for TARGET_SSE2 when + inter-unit moves to/from vector registers are enabled. Do not disable + for TARGET_MMX. + 2016-04-27 David Malcolm <dmalcolm@redhat.com> * df.h (DF_SCAN, DF_LR, DF_LIVE, DF_RD, DF_CHAIN, DF_WORD_LR, @@ -15,14 +21,19 @@ 2016-04-27 Uros Bizjak <ubizjak@gmail.com> + * config/i386/i386.c (ix86_spill_class): Enable for TARGET_SSE2 when + inter-unit moves to/from vector registers are enabled. Do not disable + for TARGET_MMX. + +2016-04-27 Uros Bizjak <ubizjak@gmail.com> + * config/i386/i386.md (lea arith with mem operand + setcc peephole2): Set operator mode. 2016-04-27 H.J. Lu <hongjiu.lu@intel.com> PR target/70155 - * config/i386/i386.c (scalar_to_vector_candidate_p): Renamed - to ... + * config/i386/i386.c (scalar_to_vector_candidate_p): Renamed to ... (dimode_scalar_to_vector_candidate_p): This. (timode_scalar_to_vector_candidate_p): New function. (scalar_to_vector_candidate_p): Likewise. @@ -652,7 +663,7 @@ directly without checking mode class. 2016-04-20 Andrew Pinski <apinski@cavium.com> - Kyrylo Tkachov <kyrylo.tkachov@arm.com> + Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/64971 * config/aarch64/aarch64.md (sibcall): Force call @@ -1078,7 +1089,7 @@ 2016-04-18 Richard Biener <rguenther@suse.de> - PR middle-end/37870 + PR middle-end/37870 * expmed.c (extract_bit_field_1): Remove broken case using a wider MODE_INT mode. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index fa23a26..84a589a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -53874,9 +53874,12 @@ ix86_get_mask_mode (unsigned nunits, unsigned vector_size) static reg_class_t ix86_spill_class (reg_class_t rclass, machine_mode mode) { - if (TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX + if (TARGET_GENERAL_REGS_SSE_SPILL + && TARGET_SSE2 + && TARGET_INTER_UNIT_MOVES_TO_VEC + && TARGET_INTER_UNIT_MOVES_FROM_VEC && (mode == SImode || (TARGET_64BIT && mode == DImode)) - && rclass != NO_REGS && INTEGER_CLASS_P (rclass)) + && INTEGER_CLASS_P (rclass)) return ALL_SSE_REGS; return NO_REGS; } |