diff options
| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2019-02-10 09:00:43 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2019-02-10 09:00:43 +0000 |
| commit | 93c75052c4b6b3754d9f868f849645ab5f7a0de2 (patch) | |
| tree | f399f1ae4344871914b90aac4d8278eaf6690215 /gcc | |
| parent | 22cdea54ade93c2c022f1dd07f81d2f624851a05 (diff) | |
| download | gcc-93c75052c4b6b3754d9f868f849645ab5f7a0de2.zip gcc-93c75052c4b6b3754d9f868f849645ab5f7a0de2.tar.gz gcc-93c75052c4b6b3754d9f868f849645ab5f7a0de2.tar.bz2 | |
[NDS32] Have nds32_spilt_doubleword to split POST_INC.
gcc/
* config/nds32/nds32-md-auxiliary.c (nds32_spilt_doubleword): Support
to split POST_INC.
From-SVN: r268738
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32-md-auxiliary.c | 50 |
2 files changed, 37 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b43a668..4418335 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-02-10 Chung-Ju Wu <jasonwucj@gmail.com> + + * config/nds32/nds32-md-auxiliary.c (nds32_spilt_doubleword): Support + to split POST_INC. + 2019-02-09 Jan Hubicka <hubicka@ucw.cz> * ipa-visibility.c (localize_node): Also do not localize diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c index 1a9cda5..3c510cf 100644 --- a/gcc/config/nds32/nds32-md-auxiliary.c +++ b/gcc/config/nds32/nds32-md-auxiliary.c @@ -3163,16 +3163,30 @@ nds32_spilt_doubleword (rtx *operands, bool load_p) /* generate low_part and high_part memory format: low_part: (post_modify ((reg) (plus (reg) (const 4))) high_part: (post_modify ((reg) (plus (reg) (const -12))) */ - low_part[mem] = gen_frame_mem (SImode, - gen_rtx_POST_MODIFY (Pmode, sub_mem, - gen_rtx_PLUS (Pmode, - sub_mem, - GEN_INT (4)))); - high_part[mem] = gen_frame_mem (SImode, - gen_rtx_POST_MODIFY (Pmode, sub_mem, - gen_rtx_PLUS (Pmode, - sub_mem, - GEN_INT (-12)))); + low_part[mem] = gen_rtx_MEM (SImode, + gen_rtx_POST_MODIFY (Pmode, sub_mem, + gen_rtx_PLUS (Pmode, + sub_mem, + GEN_INT (4)))); + high_part[mem] = gen_rtx_MEM (SImode, + gen_rtx_POST_MODIFY (Pmode, sub_mem, + gen_rtx_PLUS (Pmode, + sub_mem, + GEN_INT (-12)))); + } + else if (GET_CODE (sub_mem) == POST_INC) + { + /* memory format is (post_inc (reg)), + so that extract (reg) from the (post_inc (reg)) pattern. */ + sub_mem = XEXP (sub_mem, 0); + + /* generate low_part and high_part memory format: + low_part: (post_inc (reg)) + high_part: (post_inc (reg)) */ + low_part[mem] = gen_rtx_MEM (SImode, + gen_rtx_POST_INC (Pmode, sub_mem)); + high_part[mem] = gen_rtx_MEM (SImode, + gen_rtx_POST_INC (Pmode, sub_mem)); } else if (GET_CODE (sub_mem) == POST_MODIFY) { @@ -3189,14 +3203,14 @@ nds32_spilt_doubleword (rtx *operands, bool load_p) /* Generate low_part and high_part memory format: low_part: (post_modify ((reg) (plus (reg) (const))) high_part: ((plus (reg) (const 4))) */ - low_part[mem] = gen_frame_mem (SImode, - gen_rtx_POST_MODIFY (Pmode, post_mem, - gen_rtx_PLUS (Pmode, - post_mem, - post_val))); - high_part[mem] = gen_frame_mem (SImode, plus_constant (Pmode, - post_mem, - 4)); + low_part[mem] = gen_rtx_MEM (SImode, + gen_rtx_POST_MODIFY (Pmode, post_mem, + gen_rtx_PLUS (Pmode, + post_mem, + post_val))); + high_part[mem] = gen_rtx_MEM (SImode, plus_constant (Pmode, + post_mem, + 4)); } else { |