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| author | Richard Earnshaw <rearnsha@arm.com> | 1999-09-09 14:30:54 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 1999-09-09 14:30:54 +0000 |
| commit | 92a432f4dd29ddf98645b66f406f620d00374608 (patch) | |
| tree | d15bbd89abfdeded85fa562bf166306be03f140a /gcc | |
| parent | 6e9d618910d41d1096ff6de4fcfb8545988e60f7 (diff) | |
| download | gcc-92a432f4dd29ddf98645b66f406f620d00374608.zip gcc-92a432f4dd29ddf98645b66f406f620d00374608.tar.gz gcc-92a432f4dd29ddf98645b66f406f620d00374608.tar.bz2 | |
arm.c: Include "ggc.h".
* arm.c: Include "ggc.h".
(arm_add_gc_roots): New function.
(arm_override_options): Call it.
(aof_pic_entry): Add a GC root for aof_pic_label when it's allocated.
* arm.md (define_asm_attributes): Add a pool_range attribute.
From-SVN: r29235
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 19 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 5 |
3 files changed, 32 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 56c5145..f42c44f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +Thu Sep 9 15:24:59 BST 1999 Richard Earnshaw <rearnsha@arm.com> + + * arm.c: Include "ggc.h". + (arm_add_gc_roots): New function. + (arm_override_options): Call it. + (aof_pic_entry): Add a GC root for aof_pic_label when it's allocated. + + * arm.md (define_asm_attributes): Add a pool_range attribute. + Thu Sep 9 12:32:57 BST 1999 Nathan Sidwell <nathan@acm.org> * extend.texi (Volatiles): New node. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 69ec6fd..4ea3c05 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -39,6 +39,7 @@ Boston, MA 02111-1307, USA. */ #include "expr.h" #include "toplev.h" #include "recog.h" +#include "ggc.h" /* The maximum number of insns skipped which will be conditionalised if possible. */ @@ -72,6 +73,7 @@ static void emit_multi_reg_push PROTO ((int)); static void emit_sfm PROTO ((int, int)); static enum arm_cond_code get_arm_condition_code PROTO ((rtx)); static int const_ok_for_op RTX_CODE_PROTO ((HOST_WIDE_INT, Rcode)); +static void arm_add_gc_roots PROTO ((void)); /* True if we are currently building a constant table. */ int making_const_table; @@ -585,7 +587,20 @@ arm_override_options () max_insns_skipped = 6; else if (arm_is_strong) max_insns_skipped = 3; + + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); +} + +static void +arm_add_gc_roots () +{ + ggc_add_rtx_root (&arm_compare_op0, 1); + ggc_add_rtx_root (&arm_compare_op1, 1); + ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */ + /* XXX: What about the minipool tables? */ } + /* Return 1 if it is possible to return using a single instruction */ @@ -6725,6 +6740,10 @@ aof_pic_entry (x) if (aof_pic_label == NULL_RTX) { + /* We mark this here and not in arm_add_gc_roots() to avoid + polluting even more code with ifdefs, and because it never + contains anything useful until we assign to it here. */ + ggc_add_rtx_root (&aof_pic_label, 1); /* This needs to persist throughout the compilation. */ end_temporary_allocation (); aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 953eec7..e51f9a5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -62,9 +62,12 @@ (define_attr "pool_range" "" (const_int 0)) ; An assembler sequence may clobber the condition codes without us knowing +; If such an insn references the pool, then we have no way of knowing how, +; so use the most conservative value for pool_range. (define_asm_attributes [(set_attr "conds" "clob") - (set_attr "length" "4")]) + (set_attr "length" "4") + (set_attr "pool_range" "250")]) ; TYPE attribute is used to detect floating point instructions which, if ; running on a co-processor can run in parallel with other, basic instructions |