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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2013-09-13 10:26:34 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2013-09-13 10:26:34 +0000 |
| commit | 86eb4bd7266d96a6eee4776cab54da2f045a82d8 (patch) | |
| tree | 81dde82d2c47ad71e1041711def8c8aa5b7d38c2 /gcc | |
| parent | 83a95546b8a9e83cf5e0232ea773a95dd4a2cc78 (diff) | |
| download | gcc-86eb4bd7266d96a6eee4776cab54da2f045a82d8.zip gcc-86eb4bd7266d96a6eee4776cab54da2f045a82d8.tar.gz gcc-86eb4bd7266d96a6eee4776cab54da2f045a82d8.tar.bz2 | |
arm.md (arm_cmpsi_insn): Split rI alternative.
2013-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
Set type attribute correctly. Set predicable_short_it attribute.
(cmpsi_shiftsi): Remove %? from output template.
From-SVN: r202560
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 14 |
2 files changed, 14 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ba29299..6d8c030 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm.md (arm_cmpsi_insn): Split rI alternative. + Set type attribute correctly. Set predicable_short_it attribute. + (cmpsi_shiftsi): Remove %? from output template. + 2013-09-13 Richard Biener <rguenther@suse.de> * tree-loop-distribution.c (struct rdg_component, diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0f95804..b094cff 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8239,19 +8239,21 @@ (define_insn "*arm_cmpsi_insn" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r") - (match_operand:SI 1 "arm_add_operand" "Py,r,rI,L")))] + (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r,r") + (match_operand:SI 1 "arm_add_operand" "Py,r,r,I,L")))] "TARGET_32BIT" "@ cmp%?\\t%0, %1 cmp%?\\t%0, %1 cmp%?\\t%0, %1 + cmp%?\\t%0, %1 cmn%?\\t%0, #%n1" [(set_attr "conds" "set") - (set_attr "arch" "t2,t2,any,any") - (set_attr "length" "2,2,4,4") + (set_attr "arch" "t2,t2,any,any,any") + (set_attr "length" "2,2,4,4,4") (set_attr "predicable" "yes") - (set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")] + (set_attr "predicable_short_it" "yes,yes,yes,no,no") + (set_attr "type" "alus_imm,alus_reg,alus_reg,alus_imm,alus_imm")] ) (define_insn "*cmpsi_shiftsi" @@ -8261,7 +8263,7 @@ [(match_operand:SI 1 "s_register_operand" "r,r,r") (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))] "TARGET_32BIT" - "cmp%?\\t%0, %1%S3" + "cmp\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") (set_attr "arch" "32,a,a") |