rs6000.md (sync_add<mode>_internal, [...]): Use "bne- $-xxx" rather than local labels.

	* config/rs6000/rs6000.md (sync_add<mode>_internal,
	sync_addshort_internal, sync_sub<mode>_internal, sync_andsi_internal,
	sync_anddi_internal, sync_boolsi_internal, sync_booldi_internal,
	sync_boolc<mode>_internal, sync_boolc<mode>_internal2,
	sync_boolcc<mode>_internal, sync_lock_test_and_set<mode>): Use
	"bne- $-xxx" rather than local labels.
	(sync_lock_release<mode>): Add second operand.
	(lwsync): Use .long rather than a more meaningful opcode.
	* doc/md.texi (Standard Names): Add description of second
	parameter to sync_lock_test_and_set.

From-SVN: r98602

3 files changed, 49 insertions, 29 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 56b788d..37f9d49 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2005-04-22  Geoffrey Keating  <geoffk@apple.com>
+
+	* config/rs6000/rs6000.md (sync_add<mode>_internal,
+	sync_addshort_internal, sync_sub<mode>_internal, sync_andsi_internal,
+	sync_anddi_internal, sync_boolsi_internal, sync_booldi_internal,
+	sync_boolc<mode>_internal, sync_boolc<mode>_internal2,
+	sync_boolcc<mode>_internal, sync_lock_test_and_set<mode>): Use
+	"bne- $-xxx" rather than local labels.
+	(sync_lock_release<mode>): Add second operand.
+	(lwsync): Use .long rather than a more meaningful opcode.
+	* doc/md.texi (Standard Names): Add description of second
+	parameter to sync_lock_test_and_set.
+
 2005-04-23  Kazu Hirata  <kazu@cs.umass.edu>
 
 	PR tree-optimization/21088
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index aabe7cb..3c3e4c7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14776,7 +14776,7 @@
 	(unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
    (clobber (match_scratch:CC 4 "=&x"))]
   "TARGET_POWERPC"
-  "sync\n0:\t<larx> %0,%y1\n\t<cmp>%I2 %0,%2\n\tbne- 1f\n\t<stcx> %3,%y1\n\tbne- 0b\n\t1:\tisync"
+  "sync\n\t<larx> %0,%y1\n\t<cmp>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
   [(set_attr "length" "28")])
 
 (define_expand "sync_add<mode>"
@@ -15012,8 +15012,8 @@
    (clobber (match_scratch:CC 4 "=&x,&x"))]
   "TARGET_POWERPC"
   "@
-   0:\t<larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b
-   0:\t<larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- 0b"
+   <larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12
+   <larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16,16")])
 
 (define_insn "*sync_addshort_internal"
@@ -15031,7 +15031,7 @@
    (clobber (match_scratch:CC 5 "=&x"))
    (clobber (match_scratch:SI 6 "=&r"))]
   "TARGET_POWERPC"
-  "0:\tlwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- 0b"
+  "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
   [(set_attr "length" "28")])
 
 (define_insn "*sync_sub<mode>_internal"
@@ -15044,7 +15044,7 @@
 		   UNSPEC_SYNC_OP))
    (clobber (match_scratch:CC 4 "=&x"))]
   "TARGET_POWERPC"
-  "0:\t<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
+  "<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16")])
 
 (define_insn "*sync_andsi_internal"
@@ -15058,10 +15058,10 @@
    (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
   "TARGET_POWERPC"
   "@
-   0:\tlwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
-   0:\tlwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- 0b
-   0:\tlwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
-   0:\tlwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
+   lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
+   lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12
+   lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
+   lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16,16,16,16")])
 
 (define_insn "*sync_anddi_internal"
@@ -15075,11 +15075,11 @@
    (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
   "TARGET_POWERPC64"
   "@
-   0:\tldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b"
+   ldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16,16,16,16,16")])
 
 (define_insn "*sync_boolsi_internal"
@@ -15092,9 +15092,9 @@
    (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
   "TARGET_POWERPC"
   "@
-   0:\tlwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
-   0:\tlwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
-   0:\tlwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
+   lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
+   lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
+   lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16,16,16")])
 
 (define_insn "*sync_booldi_internal"
@@ -15107,9 +15107,9 @@
    (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
   "TARGET_POWERPC64"
   "@
-   0:\tldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
-   0:\tldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- 0b"
+   ldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
+   ldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16,16,16")])
 
 (define_insn "*sync_boolc<mode>_internal"
@@ -15121,7 +15121,7 @@
    (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
    (clobber (match_scratch:CC 5 "=&x"))]
   "TARGET_POWERPC"
-  "0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
+  "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16")])
 
 (define_insn "*sync_boolc<mode>_internal2"
@@ -15133,7 +15133,7 @@
    (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
    (clobber (match_scratch:CC 5 "=&x"))]
   "TARGET_POWERPC"
-  "0:\t<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b"
+  "<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16")])
 
 (define_insn "*sync_boolcc<mode>_internal"
@@ -15145,7 +15145,7 @@
    (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
    (clobber (match_scratch:CC 5 "=&x"))]
   "TARGET_POWERPC"
-  "0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
+  "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
   [(set_attr "length" "16")])
 
 (define_insn "isync"
@@ -15163,24 +15163,26 @@
    (set (mem:BLK (match_scratch 4 "X"))
         (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
   "TARGET_POWERPC"
-  "0:\t<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- 0b\n\tisync"
+  "<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- $-8\n\tisync"
   [(set_attr "length" "16")])
 
 (define_expand "sync_lock_release<mode>"
-  [(use (match_operand:INT 0 "memory_operand"))]
+  [(set (match_operand:INT 0 "memory_operand")
+	(match_operand:INT 1 "any_operand"))]
   ""
   "
 {
   emit_insn (gen_lwsync ());
-  emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
+  emit_move_insn (operands[0], operands[1]);
   DONE;
 }")
 
+; Some AIX assemblers don't accept lwsync, so we use a .long.
 (define_insn "lwsync"
   [(set (mem:BLK (match_scratch 0 "X"))
         (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
   ""
-  "lwsync")
+  ".long 0x7c2004ac")
 
 
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index b29d7e0..61b8856 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -4069,14 +4069,19 @@ a compare-and-swap operation, if defined.
 
 This pattern, if defined, releases a lock set by
 @code{sync_lock_test_and_set@var{mode}}.  Operand 0 is the memory
-that contains the lock.
+that contains the lock; operand 1 is the value to store in the lock.
+
+If the target doesn't implement full semantics for
+@code{sync_lock_test_and_set@var{mode}}, any value operand which is not
+the constant 0 should be rejected with @code{FAIL}, and the true contents
+of the memory operand are implementation defined.
 
 This pattern must issue any memory barrier instructions such that the
 pattern as a whole acts as a release barrier, that is the lock is
 released only after all previous memory operations have completed.
 
 If this pattern is not defined, then a @code{memory_barrier} pattern
-will be emitted, followed by a store of zero to the memory operand.
+will be emitted, followed by a store of the value to the memory operand.
 
 @end table