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| author | Sudakshina Das <sudi.das@arm.com> | 2018-03-21 17:14:48 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi@gcc.gnu.org> | 2018-03-21 17:14:48 +0000 |
| commit | 839c95d00b92ca2d9e8e3cfac023be93bab2b5c6 (patch) | |
| tree | 2dfeb060a8f91159009d85b4fd0b03e4cde63f19 /gcc | |
| parent | 5d011fcfcdcd04a94f74eca8643cb61f824774e3 (diff) | |
| download | gcc-839c95d00b92ca2d9e8e3cfac023be93bab2b5c6.zip gcc-839c95d00b92ca2d9e8e3cfac023be93bab2b5c6.tar.gz gcc-839c95d00b92ca2d9e8e3cfac023be93bab2b5c6.tar.bz2 | |
[ARM] Fix test pr82989.c for big endian and mthumb
The test pr82989.c which was added in one of previous commits is failing for
mthumb and big-endian configurations. The aim of this test was to check that
NEON instructions are not being used for simple shift operations. The scanning
of lsl and lsr instructions and checking its counts were just too restrictive
for different configurations. So I have now simplified the test to only check
for the absence of NEON instructions.
*** gcc/testsuite/ChangeLog ***
2018-03-21 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* gcc.target/arm/pr82989.c: Change dg scan-assembly directives.
From-SVN: r258723
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr82989.c | 9 |
2 files changed, 7 insertions, 7 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4422bdf..b302528 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-03-21 Sudakshina Das <sudi.das@arm.com> + + PR target/82989 + * gcc.target/arm/pr82989.c: Change dg scan-assembly directives. + 2018-03-21 Nathan Sidwell <nathan@acm.org> PR c++/84804 diff --git a/gcc/testsuite/gcc.target/arm/pr82989.c b/gcc/testsuite/gcc.target/arm/pr82989.c index 6f74dba..8519c3f 100644 --- a/gcc/testsuite/gcc.target/arm/pr82989.c +++ b/gcc/testsuite/gcc.target/arm/pr82989.c @@ -13,26 +13,21 @@ void f_shr_imm (uint64_t *a) { *a += *a >> 32; } -/* { dg-final { scan-assembler-not "vshr*" } } */ void f_shr_reg (uint64_t *a, uint64_t b) { *a += *a >> b; } -/* { dg-final { scan-assembler-not "vshl*" } } */ -/* Only 2 times for f_shr_reg. f_shr_imm should not have any. */ -/* { dg-final { scan-assembler-times {lsr\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */ void f_shl_imm (uint64_t *a) { *a += *a << 32; } -/* { dg-final { scan-assembler-not "vshl*" } } */ void f_shl_reg (uint64_t *a, uint64_t b) { *a += *a << b; } /* { dg-final { scan-assembler-not "vshl*" } } */ -/* Only 2 times for f_shl_reg. f_shl_imm should not have any. */ -/* { dg-final { scan-assembler-times {lsl\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */ +/* { dg-final { scan-assembler-not "vshr*" } } */ +/* { dg-final { scan-assembler-not "vmov*" } } */ |