mn10300.c (notice_update_cc): Enable this code.

        * mn10300/mn10300.c (notice_update_cc): Enable this code.
        * mn10300/mn10300.h (CC_OVERFLOW_UNUSABLE): Define.
        * mn10300/mn10300.md (tstsi): Use "set_zn_c0" instead of "set"
        for cc status.
        (addsi3 pattern): Break "inc" into two different alternatives
        since "inc dn" sets cc0, but "inc an" does not.
        (multiply and divide patterns): Fix cc status.
        (bCC, inverted bCC): Restore any comparison which needs the
        overflow bits when CC_OVERFLOW_UNUSABLE is set.
        (zero and sign extensions): Fix cc status.
        (movm_store): Likewise.

From-SVN: r13337

3 files changed, 46 insertions, 20 deletions

diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 19f57c0..673ddb2 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -265,7 +265,6 @@ notice_update_cc (body, insn)
      rtx body;
      rtx insn;
 {
-#if 0
   switch (get_attr_cc (insn))
     {
     case CC_NONE:
@@ -289,6 +288,12 @@ notice_update_cc (body, insn)
       break;
 
     case CC_SET:
+      /* The insn sets all the condition codes, except v is bogus.  */
+      CC_STATUS_INIT;
+      cc_status.flags |= CC_OVERFLOW_UNUSABLE;
+      cc_status.value1 = recog_operand[0];
+      break;
+
     case CC_COMPARE:
       /* The insn is a compare instruction.  */
       CC_STATUS_INIT;
@@ -299,9 +304,10 @@ notice_update_cc (body, insn)
       /* Insn doesn't leave CC in a usable state.  */
       CC_STATUS_INIT;
       break;
+
+    default:
+      abort ();
     }
-#endif
-  CC_STATUS_INIT;
 }
 
 /* Return true if OP is a valid call operand.  */
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index d4bce39..64f0a62 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -643,6 +643,7 @@ enum reg_class {
    after execution of an instruction whose pattern is EXP.
    Do not alter them if the instruction would not alter the cc's.  */
 
+#define CC_OVERFLOW_UNUSABLE 0x200
 #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
 
 /* Compute the cost of computing a constant rtl expression RTX
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 443ee99..6ef5d30 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -30,7 +30,7 @@
 ;; none_0hit - insn does not affect cc but it does modify operand 0
 ;;	This attribute is used to keep track of when operand 0 changes.
 ;; 	See the description of NOTICE_UPDATE_CC for more info.
-;; set - insn sets flags z,n.  v,c are set to 0.
+;; set - insn sets flags z,n.  v is unusable c is set to 0.
 ;;	(c may not really be set to 0 but that's ok, we don't need it anyway).
 ;; set_zn_c0 - insn sets z,n to usable values.  v is unknown.  c may or may not
 ;;	be known (if it isn't that's ok, we don't need it anyway).
@@ -178,7 +178,7 @@
   [(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
   ""
   "cmp 0,%0"
-  [(set_attr "cc" "set")])
+  [(set_attr "cc" "set_zn_c0")])
 
 (define_insn "cmpsi"
   [(set (cc0)
@@ -213,16 +213,17 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=da,a,da,x")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
-		 (match_operand:SI 2 "nonmemory_operand" "J,L,dai,i")))]
+  [(set (match_operand:SI 0 "register_operand" "=d,a,a,da,x")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
+		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,dai,i")))]
   ""
   "@
   inc %0
+  inc %0
   inc4 %0
   add %2,%0
   add %2,%0"
-  [(set_attr "cc" "none_0hit,none_0hit,set,none_0hit")])
+  [(set_attr "cc" "set,none_0hit,none_0hit,set,none_0hit")])
 
 ;; ----------------------------------------------------------------------
 ;; SUBTRACT INSTRUCTIONS
@@ -261,7 +262,7 @@
 		 (match_operand:SI 2 "register_operand" "d")))]
   ""
   "mul %2,%0"
-  [(set_attr "cc" "set")])
+  [(set_attr "cc" "set_zn_c0")])
 
 (define_insn "divsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -269,7 +270,7 @@
 		 (match_operand:SI 2 "register_operand" "d")))]
   ""
   "ext %0\;div %2,%0"
-  [(set_attr "cc" "set")])
+  [(set_attr "cc" "set_zn_c0")])
 
 (define_expand "udivsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -289,14 +290,14 @@
 		 (match_operand:SI 2 "register_operand" "d")))]
   ""
   "divu %2,%0"
-  [(set_attr "cc" "set")])
+  [(set_attr "cc" "set_zn_c0")])
 
 (define_insn "clear_mdr"
   [(unspec_volatile [(const_int 2)] 0)
    (use (match_operand:SI 0 "register_operand" "d"))]
   ""
   "mov %0,mdr"
-  [(set_attr "cc" "clobber")])
+  [(set_attr "cc" "none")])
 
 ;; ----------------------------------------------------------------------
 ;; AND INSTRUCTIONS
@@ -460,7 +461,16 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "b%B1 0f\\n\\tjmp %0\\n0:"
+  "*
+{
+  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
+      && (GET_CODE (operands[1]) == GT
+	  || GET_CODE (operands[1]) == GE
+	  || GET_CODE (operands[1]) == LE
+	  || GET_CODE (operands[1]) == LT))
+    return 0;
+  return \"b%B1 0f\\n\\tjmp %0\\n0:\";
+}"
  [(set_attr "cc" "none")])
 
 (define_insn ""
@@ -470,7 +480,16 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "b%b1 0f\\n\\tjmp %0\\n0:"
+  "*
+{
+  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
+      && (GET_CODE (operands[1]) == GT
+	  || GET_CODE (operands[1]) == GE
+	  || GET_CODE (operands[1]) == LE
+	  || GET_CODE (operands[1]) == LT))
+    return 0;
+  return \"b%b1 0f\\n\\tjmp %0\\n0:\";
+}"
  [(set_attr "cc" "none")])
 
 ;; Unconditional and other jump instructions.
@@ -570,7 +589,7 @@
 	 (match_operand:HI 1 "register_operand" "0")))]
   ""
   "exthu %0"
-  [(set_attr "cc" "set_zn_c0")])
+  [(set_attr "cc" "none_0hit")])
 
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -578,7 +597,7 @@
 	 (match_operand:QI 1 "register_operand" "0")))]
   ""
   "extbu %0"
-  [(set_attr "cc" "set_zn_c0")])
+  [(set_attr "cc" "none_0hit")])
 
 ;;- sign extension instructions
 
@@ -588,7 +607,7 @@
 	 (match_operand:HI 1 "register_operand" "0")))]
   ""
   "exth %0"
-  [(set_attr "cc" "set_zn_c0")])
+  [(set_attr "cc" "none_0hit")])
 
 (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -596,7 +615,7 @@
 	 (match_operand:QI 1 "register_operand" "0")))]
   ""
   "extb %0"
-  [(set_attr "cc" "set_zn_c0")])
+  [(set_attr "cc" "none_0hit")])
 
 
 ;; ----------------------------------------------------------------------
@@ -669,4 +688,4 @@
   [(const_int 1)]
   ""
   "movm [d2,d3,a2,a3],(sp)"
-  [(set_attr "cc" "none")])
+  [(set_attr "cc" "clobber")])