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| author | Zhenqiang Chen <zhenqiang.chen@arm.com> | 2014-01-17 05:43:45 +0000 |
|---|---|---|
| committer | Zhenqiang Chen <zqchen@gcc.gnu.org> | 2014-01-17 05:43:45 +0000 |
| commit | 82a197a2bb8198cc98bcd10c76be89dcfb3cdf9c (patch) | |
| tree | 87e0489792b512de3446da55341db20c394cb506 /gcc | |
| parent | c68b3f5291b6588570760d247a3f5223cb087915 (diff) | |
| download | gcc-82a197a2bb8198cc98bcd10c76be89dcfb3cdf9c.zip gcc-82a197a2bb8198cc98bcd10c76be89dcfb3cdf9c.tar.gz gcc-82a197a2bb8198cc98bcd10c76be89dcfb3cdf9c.tar.bz2 | |
arm.c (arm_v7m_tune): Set max_insns_skipped to 2.
ChangeLog:
2014-01-17 Zhenqiang Chen <zhenqiang.chen@arm.com>
* config/arm/arm.c (arm_v7m_tune): Set max_insns_skipped to 2.
(thumb2_final_prescan_insn): Set max to MAX_INSN_PER_IT_BLOCK.
testsuite/ChangeLog:
2014-01-17 Zhenqiang Chen <zhenqiang.chen@arm.com>
* gcc.target/arm/its.c: New test.
From-SVN: r206698
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/its.c | 20 |
4 files changed, 35 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5b0795d..eaa1927 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-01-17 Zhenqiang Chen <zhenqiang.chen@arm.com> + + * config/arm/arm.c (arm_v7m_tune): Set max_insns_skipped to 2. + (thumb2_final_prescan_insn): Set max to MAX_INSN_PER_IT_BLOCK. + 2014-01-16 Ilya Enkovich <ilya.enkovich@intel.com> * ipa-ref.c (ipa_remove_stmt_references): Fix references diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7684db9..fc81bf6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1696,7 +1696,7 @@ const struct tune_params arm_v7m_tune = &v7m_extra_costs, NULL, /* Sched adj cost. */ 1, /* Constant limit. */ - 5, /* Max cond insns. */ + 2, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_cortex_m_branch_cost, @@ -22138,11 +22138,11 @@ thumb2_final_prescan_insn (rtx insn) int mask; int max; - /* Maximum number of conditionally executed instructions in a block - is minimum of the two max values: maximum allowed in an IT block - and maximum that is beneficial according to the cost model and tune. */ - max = (max_insns_skipped < MAX_INSN_PER_IT_BLOCK) ? - max_insns_skipped : MAX_INSN_PER_IT_BLOCK; + /* max_insns_skipped in the tune was already taken into account in the + cost model of ifcvt pass when generating COND_EXEC insns. At this stage + just emit the IT blocks as we can. It does not make sense to split + the IT blocks. */ + max = MAX_INSN_PER_IT_BLOCK; /* Remove the previous insn from the count of insns to be output. */ if (arm_condexec_count) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a85acbe..665d903 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2014-01-17 Zhenqiang Chen <zhenqiang.chen@arm.com> + + * gcc.target/arm/its.c: New testcase. + 2014-01-16 Jan Hubicka <jh@suse.cz> PR ipa/59775 diff --git a/gcc/testsuite/gcc.target/arm/its.c b/gcc/testsuite/gcc.target/arm/its.c new file mode 100644 index 0000000..5425f1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/its.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +int test (int a, int b) +{ + int r; + if (a > 10) + { + r = a - b; + r += 10; + } + else + { + r = b - a; + r -= 7; + } + if (r > 0) + r -= 3; + return r; +} +/* { dg-final { scan-assembler-times "\tit" 2 { target arm_thumb2 } } } */ |