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| author | Michael Meissner <meissner@linux.ibm.com> | 2019-06-20 17:10:51 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2019-06-20 17:10:51 +0000 |
| commit | 7ca50393b3bc1c148d865cbc32e72df22ddbc564 (patch) | |
| tree | 17e3961d93d4932a8803ed2733030aaa754a9e5f /gcc | |
| parent | 7772dbe2fad60d8be78b81e0fdce23aff1344be5 (diff) | |
| download | gcc-7ca50393b3bc1c148d865cbc32e72df22ddbc564.zip gcc-7ca50393b3bc1c148d865cbc32e72df22ddbc564.tar.gz gcc-7ca50393b3bc1c148d865cbc32e72df22ddbc564.tar.bz2 | |
rs6000.md (isa attribute): Add support for for a future processor.
2019-06-20 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.md (isa attribute): Add support for
for a future processor.
From-SVN: r272513
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 7 |
2 files changed, 11 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d4c3220..7deb9d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-06-20 Michael Meissner <meissner@linux.ibm.com> + + * config/rs6000/rs6000.md (isa attribute): Add support for + for a future processor. + 2019-06-20 H.J. Lu <hongjiu.lu@intel.com> PR target/54855 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index eb03e4d..b04c7055 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -267,7 +267,8 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any")) +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf,fut" + (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? (define_attr "enabled" "" @@ -306,6 +307,10 @@ (and (eq_attr "isa" "p9tf") (match_test "FLOAT128_VECTOR_P (TFmode)")) (const_int 1) + + (and (eq_attr "isa" "fut") + (match_test "TARGET_FUTURE")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor |