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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-09-18 19:50:45 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-09-18 12:50:45 -0700 |
| commit | 7706f2f312a87b0c8509cccc986d6372dcd2fbcf (patch) | |
| tree | 788bd7394248161c4b427da2b17af48c521508e8 /gcc | |
| parent | 101a0841b6fad201172e90f716d6c1866d7b0a36 (diff) | |
| download | gcc-7706f2f312a87b0c8509cccc986d6372dcd2fbcf.zip gcc-7706f2f312a87b0c8509cccc986d6372dcd2fbcf.tar.gz gcc-7706f2f312a87b0c8509cccc986d6372dcd2fbcf.tar.bz2 | |
i386: Restore Skylake SImode hard register store cost
On Skylake, we should move integer register to SSE register without
going through memory. This patch restores Skylake SImode hard register
store cost to 6.
gcc/
PR target/90878
* config/i386/x86-tune-costs.h (skylake_cost): Restore SImode
hard register store cost to 6.
gcc/testsuite/
PR target/90878
* gcc.target/i386/pr90878.c: New test.
From-SVN: r275906
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/x86-tune-costs.h | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr90878.c | 25 |
4 files changed, 37 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d74b19f..0a20e86 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + PR target/90878 + * config/i386/x86-tune-costs.h (skylake_cost): Restore SImode + hard register store cost to 6. + +2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + PR target/91446 * config/i386/x86-tune-costs.h (skylake_cost): Increase SImode pseudo register store cost from 3 to 6 to make it the same as diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 42c9c25..8e6f4b5 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1594,7 +1594,7 @@ struct processor_costs skylake_cost = { {4, 4, 4}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {6, 6, 3}, /* cost of storing integer registers */ + {6, 6, 6}, /* cost of storing integer registers */ 2, /* cost of reg,reg fld/fst */ {6, 6, 8}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8ea581d..48e91d9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + PR target/90878 + * gcc.target/i386/pr90878.c: New test. + +2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + PR target/91446 * gcc.target/i386/pr91446.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr90878.c b/gcc/testsuite/gcc.target/i386/pr90878.c new file mode 100644 index 0000000..18dd64b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90878.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake" } */ + +union ieee754_float + { + float f; + + struct + { + unsigned int mantissa:23; + unsigned int exponent:8; + unsigned int negative:1; + } ieee; +}; + +double +foo (float f) +{ + union ieee754_float u; + u.f = f; + u.ieee.negative = 0; + return u.f; +} + +/* { dg-final { scan-assembler-not "vcvtss2sd\[^\\n\]*\\\(%.sp\\\)" } } */ |