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| author | Michael Meissner <meissner@gcc.gnu.org> | 1992-04-20 14:05:28 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1992-04-20 14:05:28 +0000 |
| commit | 7025258008b6f19407440af1953162341518b527 (patch) | |
| tree | 2f5f36281320e5ace86bda9cc18dbd44ea2aa175 /gcc | |
| parent | f5f178e0f6d7ec7afdb59b79fa332d2e428f8f28 (diff) | |
| download | gcc-7025258008b6f19407440af1953162341518b527.zip gcc-7025258008b6f19407440af1953162341518b527.tar.gz gcc-7025258008b6f19407440af1953162341518b527.tar.bz2 | |
*** empty log message ***
From-SVN: r803
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/mips/mips.md | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1435e38..2a188ce 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -752,14 +752,14 @@ ;; 65 is the multiply/divide lo register (define_insn "divmodsi4" - [(parallel [(set (match_operand:SI 0 "register_operand" "=d") - (div:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (set (match_operand:SI 3 "register_operand" "=d") - (mod:SI (match_dup 1) - (match_dup 2))) - (clobber (reg:SI 64)) - (clobber (reg:SI 65))])] + [(set (match_operand:SI 0 "register_operand" "=d") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=d") + (mod:SI (match_dup 1) + (match_dup 2))) + (clobber (reg:SI 64)) + (clobber (reg:SI 65))] "optimize && !TARGET_DEBUG_C_MODE" "* { @@ -776,14 +776,14 @@ (set_attr "length" "13")]) ;; various tests for dividing by 0 and such (define_insn "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "register_operand" "=d") - (udiv:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (set (match_operand:SI 3 "register_operand" "=d") - (umod:SI (match_dup 1) - (match_dup 2))) - (clobber (reg:SI 64)) - (clobber (reg:SI 65))])] + [(set (match_operand:SI 0 "register_operand" "=d") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=d") + (umod:SI (match_dup 1) + (match_dup 2))) + (clobber (reg:SI 64)) + (clobber (reg:SI 65))] "optimize && !TARGET_DEBUG_C_MODE" "* { |