diff options
author | H.J. Lu <hongjiu.lu@intel.com> | 2006-05-08 03:43:07 +0000 |
---|---|---|
committer | H.J. Lu <hjl@gcc.gnu.org> | 2006-05-07 20:43:07 -0700 |
commit | 67a4b391103c8327240d71073e6d47e9fa7240fc (patch) | |
tree | a7a03ed8ac9ba3fd89baa220716806dcfd30ccd2 /gcc | |
parent | 0b913ffcd3679b7ab579592aa7ed57e512f2699c (diff) | |
download | gcc-67a4b391103c8327240d71073e6d47e9fa7240fc.zip gcc-67a4b391103c8327240d71073e6d47e9fa7240fc.tar.gz gcc-67a4b391103c8327240d71073e6d47e9fa7240fc.tar.bz2 |
re PR target/24879 ([4.1]: SSE3 monitor intrinsic doesn't work in 64bit)
gcc/
2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
inline function.
(_mm_mwait): Likewise.
* config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with
"mwait".
(sse3_monitor): Make it 32bit only.
(sse3_monitor64): New. 64bit monitor.
gcc/testsuite/
2006-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* gcc.target/i386/monitor.c: New file.
From-SVN: r113617
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 12 | ||||
-rw-r--r-- | gcc/config/i386/pmmintrin.h | 9 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 19 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/monitor.c | 27 |
5 files changed, 63 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5f35ff3..4882a20 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2006-05-07 H.J. Lu <hongjiu.lu@intel.com> + + PR target/24879 + * config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use + inline function. + (_mm_mwait): Likewise. + + * config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with + "mwait". + (sse3_monitor): Make it 32bit only. + (sse3_monitor64): New. 64bit monitor. + 2006-05-07 Volker Reichelt <reichelt@igpm.rwth-aachen.de> PR target/27421 diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h index ca29559..7dbf030 100644 --- a/gcc/config/i386/pmmintrin.h +++ b/gcc/config/i386/pmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc. +/* Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This file is part of GCC. @@ -25,7 +25,7 @@ Public License. */ /* Implemented from the specification included in the Intel C++ Compiler - User Guide and Reference, version 8.0. */ + User Guide and Reference, version 9.0. */ #ifndef _PMMINTRIN_H_INCLUDED #define _PMMINTRIN_H_INCLUDED @@ -110,7 +110,6 @@ _mm_lddqu_si128 (__m128i const *__P) return (__m128i) __builtin_ia32_lddqu ((char const *)__P); } -#if 0 static __inline void __attribute__((__always_inline__)) _mm_monitor (void const * __P, unsigned int __E, unsigned int __H) { @@ -122,10 +121,6 @@ _mm_mwait (unsigned int __E, unsigned int __H) { __builtin_ia32_mwait (__E, __H); } -#else -#define _mm_monitor(P, E, H) __builtin_ia32_monitor ((P), (E), (H)) -#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H)) -#endif #endif /* __SSE3__ */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 50eced2..ed36276 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3972,7 +3972,10 @@ (match_operand:SI 1 "register_operand" "c")] UNSPECV_MWAIT)] "TARGET_SSE3" - "mwait\t%0, %1" +;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used. +;; Since 32bit register operands are implicitly zero extended to 64bit, +;; we only need to set up 32bit registers. + "mwait" [(set_attr "length" "3")]) (define_insn "sse3_monitor" @@ -3980,6 +3983,18 @@ (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_SSE3" + "TARGET_SSE3 && !TARGET_64BIT" "monitor\t%0, %1, %2" [(set_attr "length" "3")]) + +(define_insn "sse3_monitor64" + [(unspec_volatile [(match_operand:DI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "c") + (match_operand:SI 2 "register_operand" "d")] + UNSPECV_MONITOR)] + "TARGET_SSE3 && TARGET_64BIT" +;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in +;; RCX and RDX are used. Since 32bit register operands are implicitly +;; zero extended to 64bit, we only need to set up 32bit registers. + "monitor" + [(set_attr "length" "3")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5e608d9..5da14b5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2006-05-07 H.J. Lu <hongjiu.lu@intel.com> + + PR target/24879 + * gcc.target/i386/monitor.c: New file. + 2006-05-08 Alan Modra <amodra@bigpond.net.au> * gcc.dg/pr27095.c: xfail *-*-darwin*. diff --git a/gcc/testsuite/gcc.target/i386/monitor.c b/gcc/testsuite/gcc.target/i386/monitor.c new file mode 100644 index 0000000..d98a2fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/monitor.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -msse3" } */ + +/* Verify that they work in both 32bit and 64bit. */ + +#include <pmmintrin.h> + +void +foo (char *p, int x, int y, int z) +{ + _mm_monitor (p, y, x); + _mm_mwait (z, y); +} + +void +bar (char *p, long x, long y, long z) +{ + _mm_monitor (p, y, x); + _mm_mwait (z, y); +} + +void +foo1 (char *p) +{ + _mm_monitor (p, 0, 0); + _mm_mwait (0, 0); +} |