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| author | Kito Cheng <kito.cheng@sifive.com> | 2020-03-11 17:48:10 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-03-12 00:57:19 +0800 |
| commit | 5fea87cc7902c7c03c0d3c8cf7784cd99db8315d (patch) | |
| tree | 57fd1d3b69a148a205eeb4a8a838492e9b36547f /gcc | |
| parent | cb99630f254aaec6591e0a200b79905b31d24eb3 (diff) | |
| download | gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.zip gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.tar.gz gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.tar.bz2 | |
RISC-V: Fix testsuite regression due to recent IRA changes.
After IRA changes, atomic version will use one more register, but
non-atomic still use 2 registers, however this testcase isn't testing for
atomic feature, so I decide change the testcase to always use COUNT++
to test.
ChangeLog
gcc/testsuite/
Kito Cheng <kito.cheng@sifive.com>
* gcc.target/riscv/interrupt-2.c: Update testcase and expected output.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/interrupt-2.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 11061ad..e2442fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Kito Cheng <kito.cheng@sifive.com> + + * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. + 2020-03-11 Richard Biener <rguenther@suse.de> * gcc.dg/torture/20200311-1.c: New testcase. diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-2.c index 9559007..82e3fb2 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-2.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-2.c @@ -8,10 +8,6 @@ foo2 (void) INTERRUPT_FLAG = 0; extern volatile int COUNTER; -#ifdef __riscv_atomic - __atomic_fetch_add (&COUNTER, 1, __ATOMIC_RELAXED); -#else COUNTER++; -#endif } /* { dg-final { scan-assembler-times "s\[wd\]\ta\[0-7\],\[0-9\]+\\(sp\\)" 2 } } */ |