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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-05-26 12:12:20 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-05-26 12:12:20 +0000 |
| commit | 5e4d7abeeea05faaa19d97c4693d5ae6c660a831 (patch) | |
| tree | f45799067e8c25cc5a7b171d2797792aa21d2ef6 /gcc | |
| parent | ffa8b5523261b1374a62b5d28560e0de8a4c5e75 (diff) | |
| download | gcc-5e4d7abeeea05faaa19d97c4693d5ae6c660a831.zip gcc-5e4d7abeeea05faaa19d97c4693d5ae6c660a831.tar.gz gcc-5e4d7abeeea05faaa19d97c4693d5ae6c660a831.tar.bz2 | |
SIMD operations like combine prefer to have their operands in FP registers,
so increase the cost of integer registers slightly to avoid unnecessary int<->FP
moves. This improves register allocation of scalar SIMD operations.
* config/aarch64/aarch64-simd.md (aarch64_combinez):
Add ? to integer variant.
(aarch64_combinez_be): Likewise.
From-SVN: r236770
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1cd89e..b52e581 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-05-26 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_combinez): + Add ? to integer variant. + (aarch64_combinez_be): Likewise. + 2016-05-26 Jakub Jelinek <jakub@redhat.com> * config/i386/sse.md (*vcvtps2ph_store<mask_name>): Use v constraint diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 59a578f..3318c21 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2622,7 +2622,7 @@ (define_insn "*aarch64_combinez<mode>" [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w") (vec_concat:<VDBL> - (match_operand:VD_BHSI 1 "general_operand" "w,r,m") + (match_operand:VD_BHSI 1 "general_operand" "w,?r,m") (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" "@ @@ -2638,7 +2638,7 @@ [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w") (vec_concat:<VDBL> (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz") - (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))] + (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" "@ mov\\t%0.8b, %1.8b |