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| author | Jie Zhang <jie@codesourcery.com> | 2010-07-15 02:07:53 +0000 |
|---|---|---|
| committer | Jie Zhang <jiez@gcc.gnu.org> | 2010-07-15 02:07:53 +0000 |
| commit | 5cb55204f2d2b4e1c10d9baba320f6be7d5f6631 (patch) | |
| tree | 4e31c9bcc4127d53d143a223ca6cb6c2f6b6ef29 /gcc | |
| parent | 4c4837a37465783b97c7e9410a21a0261325a397 (diff) | |
| download | gcc-5cb55204f2d2b4e1c10d9baba320f6be7d5f6631.zip gcc-5cb55204f2d2b4e1c10d9baba320f6be7d5f6631.tar.gz gcc-5cb55204f2d2b4e1c10d9baba320f6be7d5f6631.tar.bz2 | |
cortex-a8.md (cortex_a8_load_store_2): Reserve cortex_a8_issue_ls.
* config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve
cortex_a8_issue_ls.
From-SVN: r162201
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/cortex-a8.md | 10 |
2 files changed, 9 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 29db69c..3e96698 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2010-07-15 Jie Zhang <jie@codesourcery.com> + + * config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve + cortex_a8_issue_ls. + 2010-07-15 Dave Korn <dave.korn.cygwin@gmail.com> * config/i386/cygwin.h (LIBGCJ_SONAME): Update. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 156959fa..8ac754e 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -47,17 +47,15 @@ "(cortex_a8_alu0+cortex_a8_issue_ls)|\ (cortex_a8_alu1+cortex_a8_issue_ls)") -;; ...and in the case of two micro-ops. We don't need to reserve -;; cortex_a8_issue_ls here because dual issue is altogether forbidden +;; ...and in the case of two micro-ops. Dual issue is altogether forbidden ;; during the issue cycle of the first micro-op. (Instead of modelling ;; a separate issue unit, we instead reserve alu0 and alu1 to ;; prevent any other instructions from being issued upon that first cycle.) ;; Even though the load/store pipeline is usually available in either -;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This -;; reservation is therefore the same as cortex_a8_multiply_2 below. +;; ALU pipe, multi-cycle instructions always issue in pipeline 0. (define_reservation "cortex_a8_load_store_2" - "cortex_a8_alu0+cortex_a8_alu1,\ - cortex_a8_alu0") + "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\ + cortex_a8_alu0+cortex_a8_issue_ls") ;; The flow of a single-cycle multiplication. (define_reservation "cortex_a8_multiply" |