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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2016-06-03 14:33:07 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2016-06-03 14:33:07 +0200 |
| commit | 5abc59784181358f0125ac67bbff25016cadf3ff (patch) | |
| tree | 35bc0204bc73f0c29aba432c0c905b9b8fd87d4b /gcc | |
| parent | e7fc19fcb5b0413324d0ccae7a045f3ef3cc04a6 (diff) | |
| download | gcc-5abc59784181358f0125ac67bbff25016cadf3ff.zip gcc-5abc59784181358f0125ac67bbff25016cadf3ff.tar.gz gcc-5abc59784181358f0125ac67bbff25016cadf3ff.tar.bz2 | |
rs6000: Remove the ancient mfcr peepholes
These peepholes replace two mfcr;mask sequences by one mfcr;mask;mask
sequence. On modern cpus, the original mfcr's were actually mfocrf,
but the new insn is an actual heavy-weight mfcr. This is very bad
for performance.
The comment says there is a three cycle delay between two consecutive
mfcr insns. This may have been true on rios, and it's true on 604,
but on 603, 750, 7400 it is just a single cycle (on 7450 it is two).
This is also a define_peephole, and we should get rid of those.
So this patch just removes the peepholes; the benefit is marginal at
best, and it so very hurts in other cases.
* config/rs6000/rs6000.md (define_peepholes for two mfcr's): Delete.
From-SVN: r237062
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 31 |
2 files changed, 4 insertions, 31 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84e81cf..90fee17 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-06-03 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (define_peepholes for two mfcr's): Delete. + 2016-06-03 Alan Hayward <alan.hayward@arm.com> * tree-vect-stmts.c (vectorizable_call) Remove GOMP_SIMD_LANE code. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6628bc6..133eef1 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11251,37 +11251,6 @@ (const_int 0)))] "") -;; There is a 3 cycle delay between consecutive mfcr instructions -;; so it is useful to combine 2 scc instructions to use only one mfcr. - -(define_peephole - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)])) - (set (match_operand:SI 3 "gpc_reg_operand" "=r") - (match_operator:SI 4 "scc_comparison_operator" - [(match_operand 5 "cc_reg_operand" "y") - (const_int 0)]))] - "REGNO (operands[2]) != REGNO (operands[5])" - "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" - [(set_attr "type" "mfcr") - (set_attr "length" "12")]) - -(define_peephole - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (match_operator:DI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)])) - (set (match_operand:DI 3 "gpc_reg_operand" "=r") - (match_operator:DI 4 "scc_comparison_operator" - [(match_operand 5 "cc_reg_operand" "y") - (const_int 0)]))] - "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" - "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" - [(set_attr "type" "mfcr") - (set_attr "length" "12")]) - (define_mode_attr scc_eq_op2 [(SI "rKLI") (DI "rKJI")]) |